Lecture 15 and 16 - Dynamic Logic
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Transcript Lecture 15 and 16 - Dynamic Logic
CSE477
VLSI Digital Circuits
Fall 2002
Lecture 15&16: Dynamic CMOS
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE477 L15&16 Dynamic CMOS.1
Irwin&Vijay, PSU, 2002
Review: Designing Fast CMOS Gates
Transistor sizing
Progressive transistor sizing
Transistor ordering
fet closest to the output is smallest of series fets
put latest arriving signal closest to the output
Logic structure reordering
replace large fan-in gates with smaller fan-in gate network
Apply “logical effort”
Buffer (inverter) insertion
separate large fan-in from large CL with buffers
uses buffers so there are no more than four TGs in series
CSE477 L15&16 Dynamic CMOS.2
Irwin&Vijay, PSU, 2002
Review: Energy & Power Equations
E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD
Ileakage
f01 = P01 * fclock
P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage
Dynamic power
(~90% today and
decreasing
relatively)
CSE477 L15&16 Dynamic CMOS.3
Short-circuit
power
(~8% today and
decreasing
absolutely)
Leakage power
(~2% today and
increasing)
Irwin&Vijay, PSU, 2002
Review: Power and Energy Design Space
Constant
Throughput/Latency
Energy
Design Time
Variable
Throughput/Latency
Non-active Modules
Logic Design
DFS, DVS
Sizing
Active
Run Time
Clock Gating
Reduced Vdd
Multi-Vdd
(Dynamic
Freq, Voltage
Scaling)
Sleep Transistors
Leakage
+ Multi-VT
Variable VT
+ Variable VT
Multi-Vdd
CSE477 L15&16 Dynamic CMOS.4
Irwin&Vijay, PSU, 2002
In addition, the Eclipse Group’s engineers were finding
plenty of bugs in the logic of their design. … So Rasala’s
schedules slipped and slipped, and slipped again. “The
way to stay on schedule,” he said, “is to make another
one.”
The Soul of a New Machine, Kidder, pg. 246
CSE477 L15&16 Dynamic CMOS.5
Irwin&Vijay, PSU, 2002
Dynamic CMOS
In static circuits at every point in time (except when
switching) the output is connected to either GND or VDD
via a low resistance path.
fan-in of N requires 2N devices
Dynamic circuits rely on the temporary storage of signal
values on the capacitance of high impedance nodes.
requires only N + 2 transistors
takes a sequence of precharge and conditional evaluation
phases to realize logic functions
CSE477 L15&16 Dynamic CMOS.6
Irwin&Vijay, PSU, 2002
Dynamic Gate
CLK
CLK
Mp
off
Mp on
Out
In1
In2
In3
CLK
CL
PDN
1
Out
!((A&B)|C)
A
C
B
Me
CLK
off
Me on
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
CSE477 L15&16 Dynamic CMOS.8
Irwin&Vijay, PSU, 2002
Conditions on Output
Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
Inputs to the gate can make at most one transition during
evaluation.
Output can be in the high impedance state during and
after evaluation (PDN off), state is stored on CL
CSE477 L15&16 Dynamic CMOS.9
Irwin&Vijay, PSU, 2002
Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static
complementary CMOS)
should be smaller in area than static complementary CMOS
Full swing outputs (VOL = GND and VOH = VDD)
Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)
Faster switching speeds
reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
reduced load capacitance due to smaller fan-out (Cext)
no Isc, so all the current provided by PDN goes into discharging CL
Ignoring the influence of precharge time on the switching speed of
the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
CSE477 L15&16 Dynamic CMOS.10
Irwin&Vijay, PSU, 2002
Properties of Dynamic Gates, con’t
Power dissipation should be better
But power dissipation can be significantly higher due to
higher transition probabilities
extra load on CLK
PDN starts to work as soon as the input signals exceed
VTn, so set VM, VIH and VIL all equal to VTn
consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
lower CL- both Cint (since there are fewer transistors connected to
the drain output) and Cext (since there the output load is one per
connected gate, not two)
by construction can have at most one transition per cycle – no
glitching
low noise margin (NML)
Needs a precharge clock
CSE477 L15&16 Dynamic CMOS.11
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Dynamic Behavior
CLK
2.5
Out
Evaluate
In1
1.5
In2
In3
In &
CLK
0.5
In4
CLK
Out
Precharge
-0.5
0
0.5
#Trns
VOH
VOL
VM
6
2.5V
0V
VTn 2.5-VTn
CSE477 L15&16 Dynamic CMOS.12
NMH
Time, ns
NML
VTn
tpHL
1
tpLH
tp
110ps 0ns 83ps
Irwin&Vijay, PSU, 2002
Gate Parameters are Time Independent
The amount by which the output voltage drops is a
strong function of the input voltage and the available
evaluation time.
Noise needed to corrupt the signal has to be larger if the
evaluation time is short – i.e., the switching threshold is truly
time independent.
CLK
Voltage (V)
2.5
Vout (VG=0.45)
1.5
Vout (VG=0.55)
0.5
Vout (VG=0.5)
VG
-0.5
0
20
40
60
80
100
Time (ns)
CSE477 L15&16 Dynamic CMOS.13
Irwin&Vijay, PSU, 2002
Power Consumption of Dynamic Gate
CLK
Mp
Out
In1
In2
In3
CLK
CL
PDN
Me
Power only dissipated when previous Out = 0
CSE477 L15&16 Dynamic CMOS.14
Irwin&Vijay, PSU, 2002
Dynamic Power Consumption is Data Dependent
Dynamic 2-input NOR Gate
A
B
Out
0
0
1
0
1
0
1
0
0
1
1
0
Assume signal probabilities
PA=1 = 1/2
PB=1 = 1/2
Then transition probability
P01 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity can be higher in dynamic gates!
P01 = Pout=0
CSE477 L15&16 Dynamic CMOS.15
Irwin&Vijay, PSU, 2002
Issues in Dynamic Design 1: Charge Leakage
CLK
4
CLK
3
Mp
Out
1
CL
A=0
2
CLK
Evaluate
VOut
Me
Precharge
Leakage sources
Minimum clock rate of a few kHz
CSE477 L15&16 Dynamic CMOS.16
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Impact of Charge Leakage
Output settles to an intermediate voltage determined by
a resistive divider of the pull-up and pull-down networks
Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.
CLK
Voltage (V)
2.5
Out
1.5
0.5
-0.5
0
CSE477 L15&16 Dynamic CMOS.17
20
Time (ms)
40
Irwin&Vijay, PSU, 2002
A Solution to Charge Leakage
Keeper compensates for the charge lost due to the pulldown leakage paths.
Keeper
CLK
Mp
Mkp
!Out
A
CL
B
CLK
Me
Same approach as level restorer for pass
transistor logic
CSE477 L15&16 Dynamic CMOS.18
Irwin&Vijay, PSU, 2002
Issues in Dynamic Design 2: Charge Sharing
CLK
Mp
Out
A
CL
B=0
CLK
Ca
Me
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
static power consumption by
downstream gates and
possible circuit malfunction.
Cb
When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is
large enough to be below the switching threshold of
the gate it drives causing a malfunction.
CSE477 L15&16 Dynamic CMOS.19
Irwin&Vijay, PSU, 2002
Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low
during precharge and that all internal nodes are initially at 0V.)
CLK
a
Ca=15fF
B
c
Cc=15fF
A
y=ABC
!A
Load
inverter
Cy=50fF
b
!B
B
!C
C
!B
d
Cb=15fF
Cd=10fF
CLK
Vout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))
= - 2.5V*(30/(30+50)) = -0.94V
CSE477 L15&16 Dynamic CMOS.21
Irwin&Vijay, PSU, 2002
Solution to Charge Redistribution
CLK
Mp
Mkp
CLK
Out
A
B
CLK
Me
Precharge internal nodes using a clockdriven transistor (at the cost of increased
area and power)
CSE477 L15&16 Dynamic CMOS.22
Irwin&Vijay, PSU, 2002
Issues in Dynamic Design 3: Backgate Coupling
Susceptible to crosstalk due to 1) high impedance of the
output node and 2) capacitive coupling
Out2 capacitively couples with Out1 through the gate-source and
gate-drain capacitances of M4
CLK
Mp
A=0
M1
B=0
M2
CLK
Out1 =1
CL1
M6
M5
Out2 =0
M4
CL2
M3
In
Me
Dynamic NAND
CSE477 L15&16 Dynamic CMOS.23
Static NAND
Irwin&Vijay, PSU, 2002
Backgate Coupling Effect
Capacitive coupling means Out1 drops significantly so
Out2 doesn’t go all the way to ground
3
2
Out1
1
CLK
0
Out2
In
-1
0
CSE477 L15&16 Dynamic CMOS.24
2
Time, ns
4
6
Irwin&Vijay, PSU, 2002
Issues in Dynamic Design 4: Clock Feedthrough
A special case of capacitive coupling between the clock
input of the precharge transistor and the dynamic output
node
CLK
Mp
A
CL
B
CLK
Out
Me
CSE477 L15&16 Dynamic CMOS.25
Coupling between Out and
CLK input of the precharge
device due to the gatedrain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
Irwin&Vijay, PSU, 2002
Clock Feedthrough
CLK
Clock feedthrough
Out
In1
2.5
In2
1.5
In3
In4
In &
CLK
0.5
Out
CLK
-0.5
0
0.5
Time, ns
1
Clock feedthrough
CSE477 L15&16 Dynamic CMOS.26
Irwin&Vijay, PSU, 2002
Cascading Dynamic Gates
V
CLK
Mp
CLK
CLK
Mp
Out1
Out2
In
In
CLK
Me
CLK
Out1
VTn
Me
V
Out2
t
Only a single 0 1 transition allowed at the
inputs during the evaluation period!
CSE477 L15&16 Dynamic CMOS.27
Irwin&Vijay, PSU, 2002
Domino Logic
CLK
In1
In2
In3
CLK
Mp
11
10
PDN
Me
CSE477 L15&16 Dynamic CMOS.28
Out1
CLK
Mp Mkp
Out2
00
01
In4
In5
CLK
PDN
Me
Irwin&Vijay, PSU, 2002
Why Domino?
CLK
In1
Ini PDN
Inj
CLK
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
CSE477 L15&16 Dynamic CMOS.29
Irwin&Vijay, PSU, 2002
Domino Manchester Carry Chain
CLK
3
P0
3
4
Ci,0
CLK
P1
3
3
P2
3
2
P3
3
1
Ci,4
5 G0
4 G1
3 G2
2 G3
1
6
5
4
3
2
!(G0 + P0 Ci,0)
CSE477 L15&16 Dynamic CMOS.31
!(G1 + P1G0 + P1P0 Ci,0)
Irwin&Vijay, PSU, 2002
Domino Comparator
CLK
A3
A2
A1
A0
Out
B3
CSE477 L15&16 Dynamic CMOS.33
B2
B1
B0
Irwin&Vijay, PSU, 2002
Properties of Domino Logic
Only non-inverting logic can be implemented, fixes
include
can reorganize the logic using Boolean transformations
use differential logic (dual rail)
use np-CMOS (zipper)
Very high speed
tpHL
=0
static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
CSE477 L15&16 Dynamic CMOS.34
Irwin&Vijay, PSU, 2002
Differential (Dual Rail) Domino
off
CLK
Out = AB
1
on
Mp Mkp
Mkp
0
CLK
Mp
0 !Out = !(AB)
1
A
!A
!B
B
CLK
Me
Due to its high-performance, differential domino is
very popular and is used in several commercial
microprocessors!
CSE477 L15&16 Dynamic CMOS.35
Irwin&Vijay, PSU, 2002
np-CMOS (Zipper)
CLK
In1
In2
In3
CLK
Mp
11
10
Out1
!CLK
In4
In5
PDN
Me
PUN
00
01
!CLK
Me
to other
PDN’s
Out2
(to PDN)
Mp
to other
PUN’s
Only 0 1 transitions allowed at inputs of PDN
Only 1 0 transitions allowed at inputs of PUN
CSE477 L15&16 Dynamic CMOS.36
Irwin&Vijay, PSU, 2002
np-CMOS Adder Circuit
!CLK
!A1
!B1
1x
0x
!B1
!A1
!A1
0 xC
!CLK
!B1
1x
CLK
!C1
2
Sum1
!C1
!A1
!B1
CLK
!CLK
CLK
1 x!C1
0x
A0
C0
A0
B0
CLK
CSE477 L15&16 Dynamic CMOS.37
B0
A0
B0
C0
1x
!CLK
B0
A0
C0
!Sum0
0x
Irwin&Vijay, PSU, 2002
DCVS Logic
10
Out
In1
!In1
In2
!In2
on off
PDN1
off on
off on
01
!Out
PDN2
on off
PDN1 and PDN2 are mutually exclusive
CSE477 L15&16 Dynamic CMOS.39
Irwin&Vijay, PSU, 2002
DCVSL Example
!Out
Out
B
!B
A
CSE477 L15&16 Dynamic CMOS.40
!B
B
!A
Irwin&Vijay, PSU, 2002
How to Choose a Logic Style
Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing
4-input NAND
Style
# Trans
Comp Static
8
CPL*
12 + 2
domino
6+2
DCVSL*
10
Ease
1
2
4
3
Ratioed? Delay Power
no
3
1
no
4
3
no
2
2 + clk
yes
1
4
* Dual Rail
Current trend is towards an increased use of
complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.
CSE477 L15&16 Dynamic CMOS.41
Irwin&Vijay, PSU, 2002
Next Lecture and Reminders
Next lecture
Timing metrics, static sequential circuits
- Reading assignment – Rabaey, et al, 7.1-7.2
Reminders
Project prototypes due October 29th
HW4 due October 31st
Final exam scheduled
- Monday, December 16th from 10:10 to noon in TBD
CSE477 L15&16 Dynamic CMOS.42
Irwin&Vijay, PSU, 2002