Transcript Chapter 6

Pass-Transistor
Logic
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Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
Allow inputs to drive source/drain terminals as well as
gate terminals
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Example: AND Gate
B
A
B
F = AB
0
Is B redundant?
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NMOS-Only Logic
Unfortunately, NMOS passes strong 0 but weak 1 (the
situation is even worsened by body effect)
3.0
In
In
VDD
x
Out
0.5m/0.25m
0.5m/0.25m
V o lt a ge [V]
1.5m/0.25m
Out
2.0
x
1.0
0.0
0
0.5
1
1.5
2
Time [ns]
Avoid cascading multiple pass-logic (without buffering)!!!
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NMOS-only Switch
C=
A=
2.5 V
C=
A=
2.5 V
C
2.5 V
L
M
2
M
1
B
M
B
2.5 V
n
VB does not pull up to 2.5V, but 2.5V - VTN
Though smaller voltage swing causes smaller dynamic
power consumption, threshold voltage loss causes
static power consumption of following inverters
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Differential Pass Transistor Logic (DPTL)
A
A
B
B
Pass-Transistor
Network
F
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
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F=A+B
B
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A
F=AÝ
(b)
A
A
B
B
A
F=AÝ
EXOR/NEXOR
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Properties of DPTL
 Similar to DCVSL, it accepts true and complementary
inputs and produce true and complementary outputs
 Some complex gates such XORs and adders can be
realized efficiently with a small number of transistors. It also
eliminates the need for extra inverters (delay symmetric).
 DPTL is static, because the output defining nodes are
always connected to either VDD or GND via low-resistance
path (good for noise)
 Design is very modular, which makes designing a library of
gates simple. More complex gates can be built by cascading
the modules.
 Some routing overhead due to complementary input/output
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Robust Pass transistor logic: solution 1
Level Restoring Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing and no static power consumption
• Restorer adds capacitance, positive on L-H delay but negative on H-L
• Ratio problem when output transitions from H-to-L
Mr size large or small? Small for large resistance
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Restorer Sizing
3.0
V olta ge [V]
2.0
W / L =1.75/0.25
r
W /L
r
=1.50/0.25
1.0
W /L
W / L =1.0/0.25
r
r
=1.25/0.25
0.0
0
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200
300
Time [ps]
400
500
9
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Solution 2: NMOS Pass Gate with VT=0
V
DD
V
0V
DD
2.5V
V
2.5V
DD
Out
0V
Zero VTN NMOS
Source-body effect might still prevent full swing
WATCH OUT FOR LEAKAGE CURRENTS!!!
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Solution 3: Transmission Gate
C
A
C
A
B
B
C
C
C = 2.5 V
Can reach 2.5V
A = 2.5 V
B
and 0V
CL
C=0V
Transmission gate combines the best of both devices by
placing an NMOS in parallel with PMOS (most popular
approach). Also make circuit static.
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Resistance of Transmission Gate
30
2.5 V
Resistance, ohms
Rn
20
Rn
Rp
2.5 V
Vou t
Rp
10
0V
Rn || Rp
0
0.0
1.0
Vou t , V
2.0
It is therefore acceptable that the equivalent on-resistance
of Transmission Gate has a constant value (8K in this case)
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Pass-Transistor Based Multiplexer
F  ( A  S  B  S ), 10 transisto rs for complement ary implementa tion
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
A
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B
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Transmission Gate XOR
F  ( A  B  A  B), 12 transisto rs for complement ary implementa tion
B
B
M2
A
A
F
M1
M3/M4
B
B
When B=1, M1/M2 inverter, M3/M4 off, so F=AB
When B=0, M1/M2 off, M3/M4 transmission gate, so F=AB
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Delay in Transmission Gate Networks
2.5
2.5
V1
In
2.5
Vi
V i-1
C
0
2.5
C
0
V n-1
V i+1
C
0
Vn
C
C
0
(a)
R eq
R eq
V1
In
R eq
Vi
C
C
R eq
V n-1
V i+1
C
Vn
C
C
(b)
m
R eq
R eq
R eq
R eq
R eq
R eq
In
C
C C
C
C
(c)
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C C
C
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Delay Optimization
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Summary
1) Ratioed logic and pass transistor logic have their own
advantages (e.g. reduced number of transistors, save
area, simpler implementation, modular design, faster)
2) But they do not have the robustness and ease of design
as the complementary CMOS (think about the XOR gate)
3) Therefore, use them when necessary (e.g. delay, area)
4) For designs with no extreme area, complexity or speed
requirements, complementary CMOS is the
recommended design style nowdays
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Dynamic Logic
Static/dynamic
Ratioed/ratioless
Complementary/noncomplementary
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Dynamic CMOS

In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
 requires n + 2 (n+1 N-type + 1 P-type) transistors

Dynamic logic achieved a similar result as
pseudo-NMOS, but avoid short circuit and
static power consumption
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Dynamic Gate
Clk
Clk
off
Mp on
Mp
Out
In1
In2
In3
Clk
CL
PDN
Me
1
Out
((AB)+C)
A
C
B
Clk
off
Me on
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
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Conditions on Output
 Once
the output of a dynamic gate is
discharged, it cannot be charged again
until the next precharge operation.
 Inputs
to the gate can make at most one
transition during evaluation.
 Output
can be in the high impedance
state during and after evaluation (when
PDN off), this is fundamentally different
from static complementary CMOS gate
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Properties of Dynamic Gates

Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary
CMOS)

Full swing outputs (VOL = GND and VOH = VDD)

Non-ratioed - sizing of the devices does not affect
the logic levels

Faster switching speeds
 reduced load capacitance due to lower intrinsic capacitance (Cin)
 reduced load capacitance due to smaller output loading (CL)
 no Isc, so all the current provided by PDN goes into discharging CL
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Properties of Dynamic Gates

Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 higher transition probabilities
 extra load on Clk

PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL (inverter) equal to VTn
 Small low noise margin (NML)

Needs a precharge/evaluate clock
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Properties of Dynamic Gates
 Main advantage of dynamic gates are increased speed and
reduced area.
 For low input signal, no switching occurs. So L-H delay 0!!
But this neglects the influence of precharge time (try to coincides
this time with other functions to improve overall performance).
 Large size of PMOS is not recommended, due to increased
capacitance for H-L delay and clock
 For H-L, the extra evaluation transistor somewhat slows down
the gate due to extra series resistance!
 Overall, the average delay is usually improved compared to
static gates (100-150ps compared to 200ps for 4 input NAND)
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Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Evaluate
VOut
Me
Precharge
Leakage sources
Dominant component is subthreshold current
Requires a minimum clock rate!!
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Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
Small or large size for keeper? Small to avoid ratio problem
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Issues in Dynamic Design 2:
Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
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Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
reduced robustness
CA
Me
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This voltage loss can
not be recovered
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Charge Sharing
case 1) if V out < VTn
VDD
VDD

Mp
Mp
Clk
C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
Out
Out
CL
A
Ma
CL
Ma X
A
B=0
B0
X
Mb

Clk
Mb
Me
Me
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Ca
Ca
Cb
Cb
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or
Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
CL
case 2) if V out > VTn
Ca 
 ---------------------
Vout = –V DD 
 Ca + CL 
 When they are equal, it means that signal A can
turn on both terminal of Ma
 The exact case can be determined by the
capacitor ratio
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Solution to Charge Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
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Issues in Dynamic Design 3:
Backgate Coupling
 The floating high impedance of the output nodes
makes the dynamic circuit sensitive to crosstalk effect ( A
wire routed over or close to a dynamic node may couple
capacitively and destroy the state of the node)
 The other equally important form of capacitive
coupling is called backgate coupling (input coupled to
output)
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Issues in Dynamic Design 3:
Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Out2 =0
CL2
In
B=0
Clk
Me
Dynamic NAND
Static NAND
Suppose Out2=1 when Out1=1 and In=0, if In goes high,
then Out2 goes low, which couples to Out1 so that Out2
could not go all the way to GND
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Backgate Coupling Effect
Due to backgate coupling
3
2
Out1
Clk
1
In
0
Out2
-1
0
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Time, ns
6
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Issues in Dynamic Design 4: Clock
Feedthrough  A special case of capacitive
Clk
Mp
A
 So voltage of Out can rise above
VDD. The fast rising (and falling
edges) of the clock couple to Out.
B
Clk
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coupling is clock feedthrough, an
effect caused by capacitive coupling
between the clock input of the preOut
charge device and the dynamic
output node.
CL
Me
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 The danger is to possibly cause
revised-based PN junction to
become forward-biased.
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Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
1.5
In2
In3
In &
Clk
0.5
In4
Out
Clk
-0.5
0
0.5
Time, ns
1
Clock feedthrough
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