Transcript Jw_fat_doc

Vmin Estimate
Application 1: for a yield or cell failure probability (P), estimate Vmin
- - - - Model
50K-point IS
o/□/Δ MC
http://www.c2s2.org
• <5% Vmin error relative to MC (<4.7σ)
• Speed up of ~105x over MC
• Excellent agreement with IS beyond 5σ
• Speed up of ~1.7x over IS
31 March 2016 Slide 1
Yield / Cell Failure Probability Estimate
Application 2: at a VDD point, estimate the cell failure probability
B
A
- - - - Model
______ IS
o/□/Δ MC
C
D
Vmin Range Pwf / Prf / Phf
A
Pwf<<Prf
Assist Strategy
http://www.c
read assist
only 2s2.org
B
Pwf<1e-4; Prf <1e-4
moderate read and write assist
C
Pwf>1e-4; Prf >1e-4
aggressive read and write assist
D
Phf becomes significant
need assistance for hold too
31 March 2016 Slide 2
Statistical Method Summary
 Generic for hold, read and write
 Easy to use
 Run 1000 Monte Carlo simulation for SNM0 at each VDD point (e.g. 0.5, 0.6, …,
1.0V)
 Extract statistical sensitivity of SNM0 to VDD
 Use the theoretical model to estimate Vmin for a given SRAM yield or cell failure
probability
 OR estimate the cell failure probability or SRAM yield at a given VDD
 Accurate: <5.0% error relative to MC, excellent agreement with IS
 Fast: ≥105 speed-up for larger SRAMs over MC
http://www.c
 Verified with both 90nm and 45nm
node2s2.org
31 March 2016 Slide 3
SOI 0.18u Test Chip for Sub-VT SRAM
• Assess various cell structures (6T, 8T, 10T,
sym, asym)
• Assess various assist methods for
http://www.c2s2.org
read/write/hold
• In fab now
31 March 2016 Slide 4
Exploration of Low Voltage eDRAM
• Logic-based eDRAM shows
potential advantages in strong
inversion [1,2] [1] J. Barth et al. ISSCC 2007
[2] D. Somasekhar et al. ISSCC 2008
• Can eDRAM compete with
SRAM at lower voltage ?
Benefits: area, leakage
Difficulties: refresh time, write
time, smaller signal to sense
1Kb eDRAM on SOI
0.18u test chip
(CQ=9.52fF)
Negative WL can exponentially increase Tref
(VQ is discharged from 0.4V to 0.3V)
http://www.c2s2.org
Node can be charged to 0.4V with a boosted
WLVDD (>0.6V) within 100nS
31 March 2016 Slide 5