Transcript Document

An Improved “Soft” eFPGA Design
and Implementation Strategy
Victor Aken’Ova, Guy Lemieux, Resve Saleh
SoC Research Lab, University of British Columbia
Vancouver, BC Canada
Overview
• Introduction and Motivation
– Embedded FPGA (eFPGA)
• Soft Embedded FPGAs
– Configurable Architecture
• Improving Soft eFPGAs
– Tactical Standard Cells
– Structured eFPGA layout
• Results
• Summary and Conclusions
2
Introduction
• SoC designs are getting more complex and
costly
• Programmability can be built into SoCs to
amortize costs by reducing chip re-spins
Software Flexibility
No Flexibility
Hardware Flexibility
eFPGAs
3
Applications for eFPGA Fabrics
CPU
3
1
An eFPGA for CPU
acceleration
2
eFPGA for product differentiation
An eFPGA for revisions
4
Motivation
• shortcomings of existing eFPGA design
approaches
– Hard eFPGA
• Highly efficient full-custom layouts but inflexible
– Soft eFPGA
• Very flexible but inefficient standard cell layouts
• alternative approach: flexible + efficient
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“Hard” eFPGA Approach with
a library of 3 Cores
user circuit
1
RTL
?
?
3
?
2
Restrictive! overcapacity increases area and delay overheads
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The “Soft” eFPGA Approach
eFPGA RTL
Generator
auto
generated
eFPGA
ASIC flow
much less logic and routing overcapacity
Generic
7x area and 2x delay versus full-custom Standard Cells
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Some Solutions to Problems of
Existing Approaches
• retain eFPGA generator idea for flexibility
But…
• use structured approach for efficiency
• use tactical cells to reduce area + delay
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Our Improved Design Approach
“Soft++”
eFPGA RTL
Generator
auto
generated
eFPGA
Structured
ASIC FLOW
GOAL
Tactical
combine best of soft and hard approaches +Generic Cells
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Island-style eFPGA Architecture
• used island-style architecture because
– Mainstream: existing FPGA CAD tools can
can be leveraged
– can exploit its regular structure to improve
design efficiency
• Created parameterized eFPGA in VHDL
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Island-style eFPGA Architecture
L: Left Edge TILE
B: Bottom Edge TILE
C: Corner TILE
L
C
B
(a) Island-style eFPGA
(b) eFPGA Tile Layout
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Unstructured vs. Structured
eFPGA Design Approach
Fixed
Logic
Fixed Logic
Soft eFPGA
(a) unstructured eFPGA layout
tile1 tile2
tile3 tile4
(b) structured eFPGA layout
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Measured Impact of Structure
on eFPGA Quality
• Significant improvements in logic capacity
– result of a more efficient CAD methodology
• wire-only critical path delay less by 21%
•
Cut CAD design time by as much as 6X
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Architecture-specific Tactical
Cells – The Concept
• improve quality by creating few tactical
standard cells to replace generic cells
• detailed analysis of design profile should
reveal areas that yield significant gains
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Standard cell Area Breakdown for
Island-Style Architecture
other
12%
flip-flops
46%
muxes
42%
switch
16%
LUT
input
30%
mux
13% LUT
mux
39%
flip-flops and multiplexers dominate eFPGA area
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Architecture-specific Tactical
Cells – Flip-Flop vs. SRAM
~2:1 area ratio!
VDD
write
clock
bit
bitb
read
clock
D
Q
GND
(a) typical D flip-flop
(b) typical SRAM cell
An SRAM circuit has fewer transistors = less area
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Custom Layout of Standard
Cell – Flip-Flop vs. SRAM
vdd
2.5X
gnd
1X
vdd
gnd
Standard Cell Flip-flop
Tactical SRAM Cell
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Architecture-specific Tactical
Cells – CMOS vs. Pass Gate
A
S0
B
S0
S0
S0 S1
S1
VDD
A
S1
O
B
C
S0
S1
O
C
D
S0
D
decompose into NAND, INV
after extra output inverter
~4:1 area ratio!
pass tree logic uses fewer transistors and is faster
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Layout Technique for Pass-Tree
Multiplexers
vdd
n-well
n-well vdd
n-well
cutout
gnd
underutilized region
extra NMOS
(denser cell)
gnd
n-well cut-outs allow denser pass transistor tree layouts
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Architecture-specific Tactical
Cells – Cell Area
Cell
Equivalent
Custom
Standard cell Tactical cell improvement
Factor
2
Area (um2)
Area (um )
1-SRAM
61
16:1 MUX
899
2228
32:1 MUX
4-LUT
5-LUT
1875
4180
24
146
2.5
6.1
293
530
1061
7.6
3.5
3.9
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Area Impact of Tactical Standard
Cells – eFPGA Area
-58%
-85%
eFPGA
eFPGA
(a) soft
(b) soft ++
eFPGA
(c) full-custom
soft ++ ~2.4X smaller than soft = 58% area savings
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Area
Graphs of Area and Delay Savings
2.4X Better
1.6 – 2.8X full-custom area
1.1X of full-custom delay
Delay
Benchmarks
1.4X Better
Benchmarks
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Fabricated Chip Designs with
eFPGAs (180nm process)
(a) gradual architecture (b) island-style architecture
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Summary
• eFPGA area improved 58% (on average)
– 2 to 2.8X larger than full-custom equivalent
(worst case)
• eFPGA delay improved 40% (average)
– within 10% of delay of full-custom versions
• exploited the regularity of island-style
architecture to increase logic capacity
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End of Talk
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Question and Answer Slide
Soft++
hard
Area
Soft
custom
Logic Capacity
soft++ fills some of performance gap left by hard
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