Transcript STICK DIAGRAM - UniMAP Portal

LAYOUT DESIGN
RULES
EMT251
LAYERS
DESIGN RULES
DESIGN RULES
DESIGN RULES
DESIGN RULES
DESIGN RULES
DESIGN RULES
Design Rule Checkers (DRC)
Goal: identify design rule violations
 General approach: “scanline” algorithm
 Computationally intensive, especially for
large chips

Design Rule Checkers (DRC)
poly_not_fet to all_diff minimum spacing = 0.5 lambda.
Layout Versus Schematic (LVS)

Goal: Compare layout, schematic netlists
 Compare
transistors, connections (ignore
parasitics)
 Issue error if two netlists are not equivalent
 Important for large designs
Layout Versus Schematic (LVS)
VDD
=
In
Out
GND
.subckt inv in out
MN1 Out In GND GND n L
MN2 Out In VDD VDD p L=
.ends inv
Area Estimation
Length
GND
In
VDD
Width
Out
Area = Length x Width
The Challenge of Design
Start: higher level (spec)
 Finish: lower level (implementation)
 Must meet design criteria and constraints

 Design
time - how long did it take to ship a
product?
 Performance - how fast is the clock?
 Cost - NRE (Non-Recurring Engineering) +
unit cost

CAD tools - essential in modern design