Transcript Interconnessioni e parassiti

Progettazione di circuiti e sistemi VLSI
Anno Accademico 2010-2011
Lezione 9
29.4.2011
Interconnessioni e parassiti
Interconnessioni e parassiti
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Impact of Interconnect
Parasitics
• Reduce Robustness
• Affect Performance
• Increase delay
• Increase power dissipation
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
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INTERCONNECT
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Capacitive Cross Talk
X
CXY
VX
Y
CY
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Capacitive Cross Talk
Dynamic Node
V DD
CLK
CXY
Y
In 1
In 2
In 3
CY
X
PDN
2.5 V
0V
CLK
3 x 1 mm overlap: 0.19 V disturbance
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Capacitive Cross Talk
Driven Node
0.5
0.45
0.4
X
VX
RY
CXY
0.3
Y
CY
tr↑
0.35
tXY = RY(CXY+CY)
0.25
0.2
0.15
V (Volt)
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
t (nsec)
Keep time-constant smaller than rise time
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Dealing with Capacitive
Cross Talk
•
•
•
•
•
•
•
Avoid floating nodes
Protect sensitive nodes
Make rise and fall times as large as possible
Differential signaling
Do not run wires together for a long distance
Use shielding wires
Use shielding layers
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Shielding
Shielding
wire
GND
V DD
Shielding
layer
GND
Substrate (GND )
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Cross Talk and Performance
- When neighboring lines
switch in opposite direction of
victim line, delay increases
Cc
DELAY DEPENDENT UPON
ACTIVITY IN NEIGHBORING
WIRES
Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0  Vdd, Vdd  0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
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Structured Predictable
Interconnect
V
S G S V S
S
G
S
V
S
V
Example: Dense Wire Fabric ([Sunil Kathri])
Trade-off:
• Cross-coupling capacitance 40x lower, 2% delay variation
• Increase in area and overall capacitance
Also: FPGAs, VPGAs
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Encoding Data Avoids Worst-Case
Conditions
In
Encoder
Bus
Decoder
Out
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Driving Large Capacitances
V DD
V in
V out
CL
• Transistor Sizing
• Cascaded Buffers
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Using Cascaded Buffers
In
Out
1
2
0.25 mm process
Cin = 2.5 fF
tp0 = 30 ps
N
CL = 20 pF
F = CL/Cin = 8000
fopt = 3.6 N = 7
tp = 0.76 ns
(See Chapter 5)
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Optimal number of stages (lez. 5/35 ref.)
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
CL  F  Cin  f N Cin with N 
ln f
t p 0 ln F  f


t p  Nt p 0 F /   1 

  ln f ln f
t p t p 0 ln F ln f  1   f


0
2
f

ln f

1/ N

For  = 0, f = e, N = lnF



f  exp 1   f 
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Output Driver Design
Trade off Performance for Area and Energy
Given tpmax find N and f
• Area
f 1
F 1
A
 1  f  f  ...  f A 
A 
A
f 1
f 1
2
N
N 1
driver
•
Energy
min


2
Edriver  1  f  f 2  ...  f N 1 CiVDD

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min
min
F 1
C
2
2
CiVDD
 L VDD
f 1
f 1
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Output Driver Design (2)
The optimal values of N and f, for minimal tp, can
give too much area and transistors.
Increasing tpmax, the problem consists in the
solution with minimal area and optimal energy
dissipation
(see text paragraph 9.2.2)
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Delay as a Function of F and N
10,000
F = 10,000
tp/tp0
1000
p
t/0
tp
100
F = 1000
10
1
3
5
7
F = 100
9
11
Number of buffer stages N
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How to Design Large Transistors
D(rain)
Multiple
Contacts
Reduces diffusion capacitance
Reduces gate resistance
S(ource)
G(ate)
small transistors in parallel
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Bonding Pad Design
Bonding Pad
GND
100 mm
Out
VDD
In
GND
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Out
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ESD Protection
• When a chip is connected to a board, there is
unknown (potentially large) static voltage
difference
• Equalizing potentials requires (large) charge
flow through the pads
• Diodes sink this charge into the substrate –
need guard rings to pick it up.
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ESD Protection
V DD
R
D1
X
PAD
D2
C
Diode
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Chip Packaging
Bonding wire
•Bond wires (~25mm) are used
to connect the package to the chip
Chip
L
Mounting
cavity
L´
Lead
frame
• Pads are arranged in a frame
around the chip
• Pads are relatively large
(~100mm in 0.25mm technology),
with large pitch (100mm)
Pin
•Many chips areas are ‘pad limited’
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Chip Packaging
• An alternative is ‘flip-chip’:
–
–
–
–
Pads are distributed around the chip
The soldering balls are placed on pads
The chip is ‘flipped’ onto the package
Can have many more pads
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Tristate Buffers
V DD
V DD
En
En
Out
Out
In
En
In
En
Increased output drive
Out = In.En + Z.En
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Reducing the swing
tpHL = CL Vswing/2
Iav
 Reducing the swing potentially yields linear
reduction in delay
 Also results in reduction in power dissipation
 Delay penalty is paid by the receiver
 Requires use of “sense amplifier” to restore signal
level
 Frequently designed differentially (e.g. LVDS)
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INTERCONNECT
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Impact of Resistance
• We have already learned how to drive RC
interconnect
• Impact of resistance is commonly seen in
power supply distribution:
– IR drop
– Voltage variations
• Power supply is distributed to minimize the IR
drop and the change in current due to
switching of gates
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IR Introduced Noise
V DD
Фpre
I
R’
V DD - ΔV
V
X
M1
I
ΔV
ΔV
R
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Power Dissipation Trends
160
140
120
100
80
60
40
20
0

3.5
2.5
2
1.5
1


0
EV4 EV5 EV6 EV7 EV8

Supply Current
3.5
120
3
100
2.5
80
2
60
1.5
40
1
20
0.5
0
Better cooling technology needed
Supply current is increasing faster!
OnOn-chip signal integrity will be a major
issue
Power and current distribution are critical
Opportunities to slow power growth


Voltage (V)
Current (A)

0.5
140
Power consumption is increasing

3
Voltage (V)
Power (W)
Power Dissipation



Accelerate Vdd scaling
Low κ dielectrics & thinner (Cu)
interconnect
SOI circuit innovations
Clock system design
micromicro-architecture
L
o
w
κ
d i e l e c t r i c s
&
t h i n
n
e r
( C
u
)
0
EV4 EV5 EV6 EV7 EV8
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ASP DAC 2000
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Resistance and the Power
Distribution Problem
After
Before
• Requires fast and accurate peak current prediction
• Heavily influenced by packaging technology
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Power Distribution
• Low-level distribution is in Metal 1
• Power has to be ‘strapped’ in higher layers of
metal.
• The spacing is set by IR drop,
electromigration, inductive effects
• Always use multiple contacts on straps
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3 Metal Layer Approach (EV4)
3rd “coarse and thick” metal layer added to the
technology for EV4 design
Power supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
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6 Metal Layer Approach –
EV6
2 reference plane metal layers added to the
technology for EV6 design
Solid planes dedicated to Vdd/Vss
Significantly lowers resistance of grid
Lowers on-chip inductance
RP2/Vdd
Metal 4
Metal 3
RP1/Vss
Metal 2
Metal 1
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Electromigration
Limits dc-current to 1 mA/mm
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The Global Wire Problem
Td  0.377 RwCw  0.693Rd Cout  Rd Cw  RwCout 
Challenges
• No further improvements to be expected after the
introduction of Copper (superconducting, optical?)
• Design solutions
– Use of fat wires
– Insert repeaters — but might become prohibitive (power, area)
– Efficient chip floorplanning
• Towards “communication-based” design
– How to deal with latency?
– Is synchronicity an absolute necessity?
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Interconnect Projections:
Copper
• Copper is planned in full sub-0.25
mm process flows and large-scale
designs (IBM, Motorola, IEDM97)
• With cladding and other effects, Cu
~ 2.2 mW-cm vs. 3.5 for Al(Cu) 
40% reduction in resistance
• Electromigration improvement;
100X longer lifetime (IBM,
IEDM97)
– Electromigration is a limiting factor
beyond 0.18 mm if Al is used (HP,
IEDM95)
Interconnessioni e parassiti
Vias
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Diagonal Wiring
destination
diagonal
y
source
x
Manhattan
• 20+% Interconnect length reduction
• Clock speed
Signal integrity
Power integrity
• 15+% Smaller chips
plus 30+% via reduction
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Reducing RC-delay
Repeater
(chapter 5)
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Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exists
an optimal length of the wire segments between repeaters. The
delay of these wire segments is independent of the routing layer!
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