Transcript Stage XII: 20 April 2005 Short Final Presentation

Presentation #13:
Smart Cart 525
Idongesit Ebong (1-1)
Jenna Fu (1-2)
Bowei Gai (1-3)
Syed Hussain (1-4)
Jonathan Lee (1-5)
Design Manager: Myron Kwai
Stage XII: 20 April 2005
Short Final Presentation
Overall Project Objective:
Design a chip as part of a system that accommodates the growing
demand for radio frequency identification (RFID) technology while
creating a quicker, more convenient shopping experience.
Status
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Design Proposal
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Architecture Proposal
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DRC of functional blocks
LVS of functional blocks
Chip Level Layout
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Gate-level implementation simulated in Verilog
Floorplan and more accurate transistor count
Schematic Design
Component Layout
Functional Block Layout
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Behavioral Verilog simulated
Size estimates/floorplanning
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Project chosen
Verilog obtained/modified
Full chip LVS
Simulations
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Schematic with loaded inputs/outputs
ExtractedRC
Full chip simulation (both parts verified separately)
Agenda For Final Presentation
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Title Slide
Project Description (Bowei)
Marketing (Bowei)
Behavioral/Algorithmic Description (Syed)
Design Process (Jenna)
Floorplan Evolution (Jenna)
Verification (Idong)
Issues Encountered (Jonathan)
Specifications (Jonathan)
Layout (Jonathan)
Conclusions (Bowei)
Project Description
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What the heck are we doing with this chip?
Marketing
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Why should you care about our product?
Behavioral/Algorithmic Description
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Diagram through the process (visio)
Flow through the schematic/block diagram
We’ll have some cool animation of some type
Design Process
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What the heck did we do from week 1 to the
end of the semester?
Encryption (cut down from 128 to 32 bits)
Verilog  schematic  layout
Floorplan Evolution
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Show our very first floorplan and other
“important” floorplans along the way
culminating our last and final floorplan
Verification
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Use graphs/tables to show that all stages of
the design process (behavioral/structural
verilog, schematic, layout, post layout)
produce the same correct outputs
Issues Encountered
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Crap that we had to deal with this semester
Specifications
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Pin specifications
Part specifications (component transistors
counts, area, density) of encryption, multiplier,
adder, and sram
Chip specifications (overall transistors counts,
area, density)
Layout
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Layer masks (active, poly, metal1-metal4)
Full chip layout
Full chip layout with overlaid floorplan
Conclusions
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Our conclusions