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Random Number Generator March 1, 2006 Component Layout and Floorplan Layout Count: 14,300 Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator Agenda • • • • • • Status Design Decisions Verification & Simulation Review DFM & Layout Rules Critical Layouts Floorplan & Design Specs Status Former C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Currently Layout (14,300 of 34,710) Awaiting • Extraction, LVS, post-layout simulation Design Decisions • Registers Re-designed – All registers based on n-pass DFF – Reduce size, power, complexity • Reduction in instances of t-gates & inverters DFF w/ Synchronous Load & CLR Register Comparisons Type Transistors Power DFF 18 10µW HLFF 26 60µW Verification • Tested structural verilog against C code for correct result. • Tested verilog schematic against structural verilog for matching signals • Performed spectre analysis of key modules DFM & ME • The Rules – Everything is on a grid – Everything is mono-directional – All metal widths are the same – Contacts same width as metals Pros • • • • Regular Layout Enforced Standardization More Accurate Resolution Contacts match metal widths Example: Group Propagate CONS • • • • • • Harder to “cut-corners” More time-involving Increased Area Decreased Speed More Metal Layers Learning Curve Minimize Inverter Use • DFM rules make inverters the more wasteful than any other gate • No good way to make them, either waste area or avoid inverters MUX’s • Inefficient • No routing through it • BIG Completed Layouts: 3 Bit Adder Block 3 Bit Adder Block SRAM Single Bus Cell Double Bus Cell SRAM (R) SRAM (M) Updated Floorplan Putting it All Together (Updated power calculations) Component Transistor Count Area Prop Delay Power Adders (4x) 5856 (1464 each) 2700um2 (675um2 ea.) 1.44ns 575uW FSM 194 100um2 826ps 46uW SRAM 17736 (M=10458 R=7278) 8000um2 735ps W: 510uW R: 190uW Datapath w/o Adders 10924 5000um2 Total 34710 15800um2 3.3 mW 500 MHz ~6.5mW Thanks! Any Questions? (Beware the Cadence Ninja)