Transcript Average1-S10

EE115C – Spring 2010
Digital Electronic Circuits
Presentation Template
Area-Delay Optimization for a
10-bit Carry-Select Adder
Design Summary
 A) Adder block topology, B) Circuit Style

Square root carry select adder
C) WHY: about Area, about Delay, other
Faster than a linear carry select adder
Schematic
Layout size
Metric
Verify
tp_ci→co = 3.34
ns
X= 29.8um,
Y= 29.8um
tp × Area = 3.0e-12
Func: N
tp_ci→s9 = 2.68
ns
Area =
0.9mm2
Tp = [] ns
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DRC: N
LVS: N
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Critical Path Analysis
 Highlight critical path
– block diagram of design / crit-path delay equation
t-crit = t-setup + t-carry + 2sqrt(5)t-mux + t-sum
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Design Optimization
 gate level critical path
 MOS detail of gates & sizing strategy
Focused on area
 Want to make sure that the full adders and the multiplexers fit
into a square area
 Used divisible dimensions in order to ensure modular design
 Used precision (ie 0.005) placement in order to minimize area
spent on satisfying design rules
Some attention to delay
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Functionality Check
 Screenshot of relevant waveforms
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Adder Layout
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Discussion
 Three most important features of your design
– Square route carry select is faster than linear
– Used mirror adders because they use less transistors
– Organized layout makes working with it systematic
 Given another chance, 3 things you would do different
– Choose a straightforward design so the layout would be
simpler
– Spend more attention on delay/sizing up front
– Favor consistent design strategies from the beginning
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