Transcript Use CMOS Transistors to bit a 4

Use CMOS Transistors to bit
a 4-bit Adder
NAND2
Schematic
symbol
Implementation of a Full Adder
(ES210)
(carry-in)
Full Adder
• 2 Half Adder
– XOR
– AND
• OR
NAND-Based XOR Gate
schematic
symbol
NAND-Based AND Gate
schematic
symbol
NAND-Based OR Gate
schematic
symbol
Full Adder
Symbol
Test Bench For the Adder
Waveforms of the Full Adder
Four-Bit Adder
C4 is calculated last because it takes C0 8 gates to reach C4
Each FA uses 2 XOR, 2 AND and 1 OR gate.
A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.
Test Bench in Verilog
Create Config
Use Template
AMS Simulator
Model Library Setup
Use the 5 V Connect Rules
Choose Enough Levels of
Hierarchy to Save
Output of the 4-bit Adder
Open database first!