Transcript Slide 1
An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets Carlos Arthur Lang Lisbôa, Luigi Carro Future technologies, bellow 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, a different design approach must be taken. Introduction What turns soft errors into a major concern is that the higher frequencies to be reached by future circuits will lead to cycle times shorter than the duration of transient pulses caused by radiation and/or electromagnetic noise. Therefore, such pulses will have a higher probability of affecting the output of combinational circuits, as well as the values stored in memory elements. Operators and Experiments Due to the random nature of SEU induced transient errors, stochastic operators have been chosen to implement one adder and one multiplier that could withstand multiple soft errors. Instead of adding or multiplying binary coded values, those devices operate on bit streams, whose probabilities (% of bits equal to 1 in the stream) are related to the values of the operands. There is an intrinsic approximation error in the conversion, which decreases as the number of bits in the stream increases, and can be regarded as noise. • Stochastic Multiplier 1001000100001011 1000100110011010 1000000100001010 Fig. 3 – Stochastic Multiplier Circuit the output stream’s precision depends heavily on the stream length short streams do not produce precise results, and the use of this operator to implement a FIR filter has shown that it is not suitable for this kind of application, due to the small precision of the products produced. • Stochastic Adder S S11 01100010101 010111011001 sum sum 0010100110101 S S33 S S22 8,192 samples 1,048,576 samples Fig. 4 – Output of FIR Filter Using Stochastic Operators 01010101101 Fig. 1 – Stochastic Adder Circuit 111111111111111111111111111111111110000000...0000 (35 1s) Conclusions and Future Work new version of adder with zero errors 111111111111111111111010101010101010000000...0000 (28 1s) new version of multiplier under development new version of multiplier: precise and tolerant to 111111111111111111110000000000000000000000...0000 (21 1s) 2 x count of 1s in the output = 56 Fig. 2 – Stochastic Adder Operation with pS3 = 0.5 Table 1. % Errors in 1,000 additions multiple simultaneous upsets up to 8 “net” flips, with 4 redundant bits in the product up to 32 “net” flips, with 6 redundant bits in the product Porto Alegre - RS BRAZIL Universidade Federal do Rio Grande do Sul - UFRGS Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) Laboratório de Sistemas Embarcados (LSE) http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse Phone +55 51 33166155 e-mail [email protected] [email protected]