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Fault Tolerance Against Multiple SEUs using Memory-Based Circuits to Improve the AVF Eduardo L. Rhod, Álisson Michels, Carlos A. L. Lisbôa, Luigi Carro ETS 2006 Technology trends for semiconductors forecast a higher incidence of soft errors caused by radiation in digital circuits implemented using sub 65nm technologies. New design approaches are necessary to generate circuits that are able to withstand multiple simultaneous upsets. Traditional fault tolerance approaches like TMR do not support multiple SEUs. Results show that even N-MR techniques do not work as expected. Several error detection and correction codes have been proposed, but most of them do not correct multiple bit flips, or when they do, the overhead in area and / or performance is not acceptable. Introduction Case Study: 4-tap, 8-bit FIR filter Memories using emerging technologies, like magnetic RAMs, are not affected by high energy particle strikes. This work proposes to replace parts of combinational circuits with intrinsically protected memories, thus reducing the overall architectural vulnerability factor (AVF), and, consequently, the soft error rate (SER). 1 IN0 1 IN1 ROM MEMORY (COEFFICIENTS) 1 IN2 1 IN3 10 Replacing combinational circuits with memory 10 (the memory works as a truth table !) Example: 4x4-bit multiplier Combinational only Memory only + Circuit sensitive to faults REGISTER 10 10 8 inputs and 8 outputs Input A Input B 4 y[17] ..... y[8] 8 Result Memory 4 11 y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] Results 4x4-bit Multiplier AVF and Timing for Single and Double Faults Total area = 2,048 transistors (considering 1 transistor per bit) Case Study: 4x4-bit Multiplier 1) Column Multiplier 0 A0 A1 A2 A3 0 0 0 B0 0 0 A0 A1 A2 A3 0 0 Circuit sensitive to faults P6 B1 0 0 0 A0 A1 A2 A3 0 Memory P5 P4 P3 P2 P1 P0 P7 Result ShiftRegister Counter for mux selection signals B3 492 8.80 20.50 8.80 20.50 18.5 TMR 268 5.49 16.26 2.99 8.86 18.2 Combin. 76 49.11 63.60 7.59 9.82 17.5 Column 33 15.92 28.05 1.07 1.88 15.0 Line 9 36.22 54.07 0.66 0.99 16.5 #of gates that fail Prop. AVF % (1 fault) Prop. AVF % (2 faults) Critical Path Timing (ns) Combinational 1631 48.21 67.35 69.0 Memory Based 50 1.39 2.11 7.1 Conclusions 3 P3 2) Line Multiplier P2 P1 P0 A0 Memory A2 Experiments have shown that the proposed technique reduces the AVF up to 30 times. The bad results for the 5-MR solution are due to the increased unprotected circuit area for voters, when compared to TMR. A1 A3 Circuit sensitive to faults Counter for mux selection signals 5-MR Circuit Circuit Register B0 B1 B2 B3 AVF % (1 fault) FIR Filter AVF and Timing for Single and Double Faults B2 0 0 0 0 A0 A1 A2 A3 #of gates that fail Expensive !!! Total area = 304 transistors Prop. AVF Prop. AVF AVF % % (1 % (2 (2 faults) fault) faults) Critical Path Timing (ns) P7 P6 P5 P4 Future Work Test the proposed approach with different case studies Use this technique to implement a memory-based processor 4 bit Register Result ShiftRegister Porto Alegre - RS BRAZIL Universidade Federal do Rio Grande do Sul - UFRGS Programa de Pós-Graduação em Engenharia Elétrica Programa de Pós-Graduação em Computação http://www.ufrgs.br/ppgee, http://www.inf.ufrgs.br/pos/ppgc e-mail [email protected] [email protected] [email protected] [email protected]