Transcript Using Memory to Cope with Simultaneous Transient Faults

Universidade Federal do Rio Grande do Sul
Programa de Pós-Graduação em Engenharia
Elétrica
Using Memory to Cope with
Simultaneous Transient Faults
Authors:
Eduardo L. Rhod ([email protected])
Carlos A. L. Lisbôa ([email protected])
Luigi Carro ([email protected])
The Problem
• Due to the technology scaling, future (an actual) technologies will
be heavily influenced by electromagnetic noise causing SEU and
SET inducted errors;
• The ocurence of multiple SEU and SET, which was not a
problem in the past, must have to be considered;
• We must guarantee robustness at lowest cost;
• Some usual protection techniques like TMR and N-MR might not
work properly;
2
Motivations
• Memory comes with intrinsic protection
against manufacturing errors (spare
columns and spare rows);
• There are protection techniques with low
area and latency overhead like Reed
Solomon that can be applied;
3
Our Proposal
• Use Reed-Solomon protected memory to
replace combinational circuit;
• Reducing the area sensible to faults;
• Reducing the SER (soft error rate) of the
circuit;
4
Outline
• Case Studies;
• Results;
• Conclusions;
• Future Work.
5
Replacing Combinational Circuit by
Memory (ROM memory)
• Example:
4x4 bit multiplier
- Fully combinational:
FullyEXPENSIVE
memory:
8 inputs and 8 outputs
28 x 8 = 2,048 bits
Input A
4
Input B
Memory
result
8
4
Total area = 304 transistors
Total area = 2,048 transistors
considering 1 transistor per bit
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Replacing Combinational Circuit by
Memory (ROM memory)
• Example:
Let’s Replace just some part of the circuit !!!
4x4 bit multiplier
1 column
- Fully combinational:
7 inputs and 4 outputs
27 x 4 = 512 bits
4
Memory
512 bits
Total area = 304 transistors
Area cost = 512 transistors
Latency = 7 cycles
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Case Studies
4x4 bit multiplier
Two memory based solutions were
proposed:
• Column multiplier;
• Line multiplier;
These two solutions were compared
with the TMR and N-MR techniques.
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Case Studies
4 taps 8 bit FIR Filter
Memory based solution
compared with the combinational one
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Case Studies
4x4 bit multiplier
- Column Solution
Sensitive to Faults
Protected by RS code
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Case Studies
4x4 bit multiplier
Sensitive to Faults
- Line Solution
Protected by RS code
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Case Studies
8-bits FIR Filter with 4 taps Protected by RS code
• Just using memory:
Input 1
8
Memory size
24*8 x 18 = 77 Gb
Input 2
8
Input 3
8
• Memory + comb sol.:
Input 4
8
Memory
With coef.
Result
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Memory size
24 x 10 = 160 bits
Latency = 8 cycles
Sensitive
to faults
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Fault Injection Process
Fault injection Steps:
•
Run the circuit fault free with the 1st input;
•
Run the circuit with “single event level 0” at the 1st
gate;
•
Compare the fault free and the “single event level 0”
results to detect if the fault have propagated;
•
Run the circuit with “single event level 1” at the 1st
gate;
•
Compare the fault free and the “single event level 1”
results to detect if the fault have propagated;
•
Repeat the process for all gates;
•
Repeat the process for all inputs;
•
Repeat the process for double faults;
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Results
4x4 Bit Multiplier Fault Rate Results for SINGLE Fault Injection
The voter
Is too big
Circuit
Total
Area
# of gates
that fail
Latency
(ns)
Fault rate
(%)
Proportional
fault rate (%)
5-MR
2128
532
18.5
8.80
8.80
TMR
1072
262
18.2
5.49
2.77
Combinational
304
76
17.5
49.02
7.00
Column
2004
33
120
46.82
2.90
3x
Line
4252
9
66
70.23
1.19
7x
2 x more area
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Results
4x4 Bit Multiplier Fault Rate Results for DOUBLE Fault Injection
The voter
Circuit
Total
# of gates
Latency
Proportional
Is too big
Area
that fail
fault rate (%)
(ns)
5-MR
2128
532
18.5
20.50
TMR
1072
262
18.2
8.19
Combinational
304
76
17.5
8.95
Column
2004
33
120
4.19
5x
2
Line
4252
9
66
1.53
13x x
5
24 x more area
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Results
FIR Filter Fault Rate Results for SINGLE Fault Injection
Circuit
Total Area
# of gates
that fail
Latency
(ns)
Proportional
fault rate (%)
Combinational
6524
1631
69
48.21
Memory
1832
50
56.8
2.58
18 x
FIR Filter Fault 3.5
Rate
Results
x less
area for DOUBLE Fault Injection
Circuit
Total Area
# of gates
that fail
Latency
(ns)
Proportional
fault rate (%)
Combinational
6524
1631
69
67.35
Memory
1832
50
56.8
2.96
22.5 x
16
3.5 x less area
Conclusions
• This work showed that replacing combinational circuit by
memory based circuit can be used to improve circuit
reliability against single and double faults, with some
penalties in area and computational time;
• The presented technique, permits different memory
based solutions with different costs and gains;
• Results showed that 5-MR technique may not work as
expected.
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Future Work
• Implement this technique using magnetic
memory (no area overhead);
• Test the presented approach with different case
studies;
• Develop a tool that chooses between different
memory based solutions, which best fit for each
application;
• Implement this technique to develop a memory
based processor.
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Thank You !!!
Questions ???
e-mails:
Eduardo L. Rhod ([email protected])
Carlos A. L. Lisbôa ([email protected])
Luigi Carro ([email protected])
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Fault Injection Process
Tools:
4x4 bit multiplier
•
Caco-ps – Cycle Accurate Configurable Power Simulator
- combinational;
- column;
- line;
•
Synthesized solutions* (for more than 100 gates failing):
- TMR;
- 5-MR;
FIR Filter
- combinational;
- memory based;
*using Altera FPGA EP20K200EFC484-2X.
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