Transcript SecurOne * Final Design Presentation

Wednesday 2nd December, 2009
Group M1
Insik Yoon
Mehul Jain
Umang Shah
SritejaTangeda
Team Manager
Prajna Shetty
Secure unique Smart Card Reader
Outline
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Motivation for the Smart Card with applications
Potential for the Card
What is SecurOne?
Applications
Market Potential
Project description
Basic Functional blocks
Behavioral description
Design Process
Floorplans
Layout
Verification
Conclusion
Motivation for the Smart Card
• Smart Card:
– identification, authentication, and data storage.
– a means of effecting business transactions.
– strong authentication for multiple application access.
• Potential competitors:
– Karta Miejska (Warsaw, Poland)
– Navigo card(Paris, France)
– YTV travel card (Helsinki, Finland) , etc.
• Greater security demand!
Smart Card Applications
• Identification
– Passport details, driver’s license information, school ID .
• Billing
– Any Credit & debit card applications.
• Ticketing information
– Bus / Train rides.
– Tourists Attractions and Sporting Events.
– Discount in groceries / department stores.
• RFID tag reader
– Highway pass detection.
Market potential for such a
card
• Huge target market :
– If used as a national ID, there are 217.8 million people above
the age of 18 in the United States alone.
– Ease of transaction to 181 million people (by 2010) with credit
cards in the United States only.
• India is trying to introduce a Unique ID for all its
citizens. This can be targeted as a potential starting
point for this product.
– Potential billion customers.
However….
• We need Hardware to access / modify information on
the card.
• This calls for a Reader which can do the above functions
in a secure way.
Goal
• Make a smart card reader which has an encryptor and a
decryptor along with a fingerprint matching feature to
access / modify data on card.
What is SecurOne?
A card reader for a potential Universal Smart Card
which stores information such as ID, credit information
and others.
Key features:
• More secured way of accessing critical information
(finger print matching along with encryption).
• Details can be modified through the internet and
updated through an easily accessible card reader.
• A unified approach for all these requirements while
ensuring proper security.
Applications
• Read / update information on the card for
– Bus / Train rides.
– Tourists Attractions and Sporting Events.
– Discount in groceries / department stores.
• Encrypt/Decrypt the card information
• Fingerprint matching with the user.
Market Potential
• Will handle a lot of sensitive information.
– Security is a major issue.
– And we provide it through encrypted information and
finger print matching.
• User can update information stored on the card
– The card readers currently present in the market can
only read the data stored on a card.
– SecurOne enables active interaction between card and
a user.
Outline
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•
•
•
•
•
•
•
•
•
•
•
•
Motivation for the Smart Card with applications
Potential for the Card
What is SecurOne?
Applications
Market Potential
Project description
Basic Functional blocks
Behavioral description
Design Process
Floorplans
Layout
Verification
Conclusion
Project description
SecurOne Smart Card Reader
• Obtain and compare the finger print data from the card
and the user.
• Perform the following functions in a secured method:
– Update
– Display
– Transaction
Top View-SecurOne
Basic Functional Blocks
• Encryption/Decryption Block
– 16-bit TEA Encryption and Decryption
• Comparator
– 16-bit Comparator
• FSM for Operations
–
–
–
–
–
Main FSM
Init FSM
Update FSM
Transaction FSM
Display FSM
• SRAM for all the data storage
– 32-bit, 16-bit and 5-bit SRAMs
Encryption and Decryption
• Used TEA(Tiny Encryption Algorithm)
encryption algorithm for encrypting
the data to be stored on the card.
• The encryption and decryption was
performed using 10 computation cycles.
• Data Required:
– Plain text (encryptor) : 16 bits
– Key : 32 bit (4 sub-keys each 8 bits long)
– Delta : 16 bit magic number
• Algorithm:
V0+ = ((V1<<4)+k0)^(V1+sum)^((V1>>5)+k1)
V1+ = ((V0<<4)+k2)^(V0+sum)^((V0>>5)+k3)
Initial FSM Flow Chart
1
B
Card Reader
1
A
C 16
Decryptor
External Blocks
Computational
and Memory Blocks
FSM Blocks
D
Control
Unit
Initial
1
C
1
1
E
B
1
G
1
Finger Print
Reader
C
1
16
E
16
SRAM 4 BYTE
Finger Print Data
F
Co
mp
16 F
16
F
Init  Main  Update
Control
Unit
Initial
A
1
Main
Menu
FSM
B
2
1
C
Display Unit
User
C={00}
Control
Unit
Update
Control
Unit
Display
Control
Unit
Trans.
Control
Unit
Exit
Update FSM Flow Chart
5
H
16
H
Smart Card
I
SRAM 4 BYTE
Finger Print Data
1
1
D
1
Main
Menu
FSM
J
A
Control
Unit
Update
1
B
Display Unit
User
1
1
H
1
5
DH
1
C
C
1
SRAM 5Bit
(Choice Regfile)
F
16 E
G
Encryptor
16
Central
Server
Interface
5
E
Main  Display
Main
Menu
FSM
B
2
1
C
Display Unit
User
C={01}
Control
Unit
Update
Control
Unit
Display
Control
Unit
Trans.
Control
Unit
Exit
Display FSM Flow Chart
Main
Menu
FSM
Control
Unit
Display
1
H
1
H
Decryptor
16
F
1
A
16
1
B
1
D 1
G
16
I
K 1
I
1
SRAM 2 BYTE
Display Data
J
E
F
1
1
Smart Card
C
Display Unit
User
5
1
C
SRAM 5Bit
(Choice Regfile)
E
5
Main  Transaction
Main
Menu
FSM
B
2
1
C
Display Unit
User
C={10}
Control
Unit
Update
Control
Unit
Display
Control
Unit
Trans.
Control
Unit
Exit
Transaction FSM Flow Chart
I
16
Display Unit
Vendor
J
H
1
F
G
1
16 H
Decryptor
1 K
A
Control
Unit
Trans.
I
1
SRAM 2 BYTE
Transaction Data
1
Main
Menu
FSM
E
1
B
C
1
D
1
1
C
5
1
SRAM 5Bit
(Choice Regfile)
1
16
Display Unit
User
F Smart Card
E
5
Exit
Main
Menu
FSM
B
2
1
C
Control
Unit
Initial
Display Unit
User
C={11}
Control
Unit
Update
Control
Unit
Display
Control
Unit
Trans.
Control
Unit
Exit
Outline
•
•
•
•
•
•
•
•
•
•
•
•
•
Motivation for the Smart Card with applications
Potential for the Card
What is SecurOne?
Applications
Market Potential
Project description
Basic Functional blocks
Behavioral description
Design Process
Floorplan
Layout
Verification
Conclusion
Design Process
• Verilog
– Behavioral
– Structural
– Testing
• Schematic
• Simulation
• Layout
Verilog
• Behavioral Verilog modeling
– To test the logical functionality of the blocks, each logical block was
first designed in behavioral verilog and run through several testing
cycles.
• Final Structural Verilog version
– In order to facilitate the transition to schematic, a structural version of
the same was modeled and went through several iterations of
modifications and testing.
Schematics
• Transmission Gate Logic was avoided to have an electrically
safe circuit.
• In order to cater for the extremely regular layout design, a
careful choice of transistor sizes was required (so as to
minimize the number of different transistor sizes).
• The following transistor finger size was used:
PMOS
NMOS
750n
300n
Layouts
• The entire layout was done following the rules of Extremely
Regular Layout.
• Each transistor was custom laid and the number of different
transistor sizes was minimized.
• Poly Extension on Active was increased to improve
printability.
• Double contacts were used on poly to provide redundancy.
• Used a Poly Pitch = Metal1 Pitch = Metal3 Pitch = 0.42um.
• Used a fixed Metal2 and Metal 4 pitch of 0.5um for the
entire chip.
FLOOR-PLAN 1
Exit
Initial FSM
4 B SRAM
Main
Menu FSM
Update
FSM
Decryptor
Comparator
Choice Regfile
Display
FSM
Display SRAM 2B
Encryptor
Trans. FSM
Trans. SRAM 2B
Encryptor
16 bit
SRAM
Display
170 x 88
2.4 x 88
16 bit
SRAM
Transaction
2.4 x 88
170 x 6
Decryptor
170 x 88
Routing Channels
Main Menu
5 bit
choice
Display
2.4 x 18
5 bit
choice
Update
2.4 x 18
Update
FSM
42 x 44
5 bit
choice
Trans
2.4 x 18
Display
FSM
42 x 44
Project Evolution:
Routing Channels
Floor-plan 2
16 bit
SRAM
FP 1
16 bit
SRAM
FP 2
2.4 x 88
2.4 x 88
16 bit
Comparator
14 x 88
Transaction
FSM
42 x 44
Init
FSM
42 x 44
Encryptor
16 bit
SRAM
Display
170 x 88
2.4 x 88
16 bit
SRAM
Transaction
2.4 x 88
5 bit
choice
Display
2.4 x 18
Routing Channels
5 bit
choice
Update
2.4 x 18
Update
FSM
42 x 44
5 bit
choice
Trans
2.4 x 18
Display
FSM
42 x 44
Routing Channels
Project Evolution:
Final Floor-plan
Decryptor
170 x 88
16 bit
SRAM
FP 1
16 bit
SRAM
FP 2
2.4 x 88
2.4 x 88
16 bit
Comparator
14 x 88
Main Menu
FSM
42x 10
Transaction
FSM
42 x 35
Init
FSM
42 x 35
Final Layout – Chip Layout
16 bit
Reg-files
5 bit Regfile
Display
FSM
Transactio
n FSM
Encryptor
Main FSM
Update
FSM
Decryptor
Initial
FSM
16 bit
Reg-files
HLFF bank
Layout of Display FSM
Layout of Transact FSM
•
Layout of Main FSM
Layout of Update FSM
Layout of Init FSM
Outline
•
•
•
•
•
•
•
•
•
•
•
•
•
Motivation for the Smart Card with applications
Potential for the Card
What is SecurOne?
Applications
Market Potential
Project description
Basic Functional blocks
Behavioral description
Design Process
Floorplan
Layout
Verification
Conclusion
Verification
• Done at 2 different levels
– Functional
•
•
Behavioral Verilog
Structural Verilog
– Schematic
• The individual blocks were tested at the schematic level
before integrating them.
• Several vector tests were conducted on each block separately.
• The entire module was then integrated and tested with 5
different vector inputs.
• The module was tested with a 2 ns clock.
Verification
0
0
1
0
1
Verification
0
0
2
1
0
Verification
0
0
3
1
1
Verification
0
1
4
0
0
Verification
1
1
F
1
1
Verification
1
1
D
0
1
Verification
0
1
5
0
1
Verification
1
0
8
0
0
2ns global clock
Card insert
signal goes high,
indicating the
card is inserted.
The finger print data
from the card is
compared with the one
from the reader and if a
match occurs,
Comparator_complete
goes high.
Wordline goes
high to store the
FP data from the
reader.
User makes Main
Menu choice.
Update_ON
indicates the
control is
transferred from
the Main FSM to
update.
Verification
Main Menu Choice
00
Verification
Display_Update
signal goes high to
indicate the
update menu
being displayed.
Once the Info
arrives from
the central
server, the
control is
transferred to
the Encryptor.
Indicates the
choice of
submenu the user
wants to update.
Once the choice is
set, the
choice_ready
signal goes high.
Wordline of the
choice reg file
goes high , to
store the value of
the field that
needs to be
updated.
CS_Control
signal indicates
that the info
has been sent
by the Central
server.
Verification
Update choice sent to
the Smart Card.
Reset_update goes
high. Indicating the end
of Encryption.
This signal is used to
assert the Write-Enable
of the Smart Card.
Update_complete is
asserted to transfer
control back to the main
FSM.
Final Layout – Chip Layout
Delta
Key
Encrypted
Data
Data Into
Decryptor
Data Into
Encryptor
Decrypted
Data
Input into
Choice
Regfiles
Data from
FP Reader
Specifications
• Area =94539.1536µm2
– 502.12um x 188.28um
– 1:2.66 Aspect Ratio
• Transistors : 17236
Block
Transistor Count
Encryption/Decryption
13000
FSMs (Including SRAMS)
3616
Comparator
620
• Density
– 0.18231 transistors / µm2
• I/O’s
– 114 inputs
– 49 outputs
Conclusion
• Implemented smart card reader.
• Main components : SRAM, FSMs,
TEA encryptor/decryptor.
• Used Verilog and Cadence Spectre
simulation for verification.
• Adapted extremely regular layout
techniques.
SecurOne System
Touch
screen
Display
Power on
and
power
off
buttons.
Finger
print
scanner.
Display
Update
Transact
Exit
Flip it around to insert
the card
Thank You