Transcript Sprinkler Buddy

Sprinkler Buddy
“Low Cost Irrigation Management For Everyone !”
Kalyan Kommineni | Panchalam Ramanujan | Sasidhar Uppuluri
Kartik Murthy | Devesh Nema | Design Manager: Bowei Gai
Presentation Outline
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Marketing
Project Description
Behavior/Algorithmic Description
Design Process
Floor Plan Evolution
Layout
Verification
Issues Encountered
Specifications
Conclusions
Sprinkler Buddy at-a-glance
1.1 Billion potential customers
$52 Million market potential
100% yearly market growth
5 month payback to customer
Large and Untapped Market
• 95% of the 1.1 billion farmers are from
developing nations
• 60% of irrigation water wastage in these
nations
Drip Irrigation
The South Asian Farmer
• Earns $795.56 annually
• Purchases 4 months of water to
supplement 4 months of rain
water
• Wastes 25 % of yearly earnings
in water costs
Sprinkler Buddy: The low cost, automated solution !
Includes:
The Sprinkler Buddy Advantage
Simple ease of
use
Rain Bird
Low Power
Design
Exhaustive
Metrics
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Low Cost Solution
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Gorman-Rupp
Jain Sprinklers
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Sprinkler
Buddy
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Minimal Setup
Solar Powered Design
UN Certified Water Output Calculations
Low Cost Alternative
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UN Specified Water Equation
Water Output = KC*ETo
Look-up from table based
(P)*(.46*Tmean+8)
on type/stage of crop
Mean Daily % of Daylight Hours
(TmaxAvg+TminAvg) /2
Innovative Key Features
• Quiet Bit-line SRAM
• Semi-Clocked Control Architecture
– Broken into five distinct modes
• Power Shut Off
– Almost 60% is off during the day
Behavioral
Description
Temperature
from Sensor
Hourly Update
Hourly
Update
Current TMax and TMin
Update
DailyDaily
Update
Standby
Hourly
Clock
Main FSM
Main
FSM
(Init and PSO)
Daily
Clock
FSM Start
(HU & DU)
FP Adder
Reset
(HU & DU
& C)
Current TMax Avg and TMin Avg
Month
Computation
Computation
Crop Type
Water Output
Water At
Plant
Valve Enable
Feedback
Feedback
Water Tank
Level
Error Signal
Hourly Update Mode
-> Stores Max and Min Temperatures for each day
Temperature from Sensor
Temp Register
TMax Register
TMin Register
20:10 Mux
FP Subtractor
Add Sign
Daily Update Mode
PG SRAM en
HU TMax
HU TMin
sramInput
5 Bit
Counter
50:20 Mux
input
[19:10]
PG State
5 Bit
Counter
input
[9:0]
TMax SRAM
index
out
FP Add/Sub
Old Value Max Register
TMax Sum Register
10:5 Mux
10:5 Mux
cROMsel
cROMsel
2:1 Mux
TMin SRAM
index
out
Old Value Min Register
TMin Sum Register
20:10 Mux
20:10 Mux
count (max) count (min)
Constant ROM
15:5 Mux
11111
ch max
FP Multiplier
TMin Avg Register
Tmax Avg Register
-> Saves temperatures for past
32 days and updates averages
TMax Avg
(w/o Exp)
TMax Avg
Exp
TMin Avg
(w/o Exp)
5 Bit Add/Sub
Computation Mode
TMin Avg
Exp
-> Computes final water output
using UN FAO Equation
5 Bit Add/Sub
8
40:20 Mux
[9:0]
[19:10]
FP Adder
P ROM
Month
.46
60:20 Mux
[19:10]
KC ROM
[9:0]
FP Multiplier
Water Output Register
Crop Type
Feedback Mode
-> Enables valve until UN approved water amount has been supplied
-> Outputs an error signal in case of water shortage
Water
Output
Water At
Plant
Water At
Tank
40:20 Mux
[19:10]
[9:0]
FP Subtractor
Adder Output Register
(Add Sign)’
Valve Enable Register
Valve Enable
Add Sign
Error Signal Register
Error Signal
Main FSM
-> Initializes SRAM and manages Power Shutoff
Initialize SRAM
Standby
Hourly Clock Signal
Daily Clock Signal
Power Up Hourly Update
Power Up Daily Update
and Computation
Reset HU FP Adder
Reset Daily Update and
Computation FP Adders
Hourly Update On
Daily Update and
Computation On
Hourly Update Done
Daily Update and
Computation Done
Design Process Overview
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Emphasized low power design
– Re-use of components
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Focused on compact layout
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Used 10 bit floating point format
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Employed Semi-Clocked Design with
handoff between modes
Design Process – Verilog/Floor Plan
• Verilog:
– All changes were first verified in Verilog then
translated into schematic.
• Floor plan
– Created a detailed floor plan early on to avoid
later routing issues
– Early Floor plan iterations were completed
before schematics
Design Process – Schematic
• Selected topologies and logic styles of
components based on low power
requirements
• Shutoff power to unused components to
cut down on leakage current
• Sized buffers for optimal rise and fall times
• Removed glitches to avoid layout issues
Design Process – Layout
• Focused on maximum density to reduce
parasitics
• Simulated all intermediate layouts to
isolate problems
• Used wider interconnects for long paths
and supply rails
Floor Plan Progression
Layout - FPUs
FP Multiplier
FP Adder
Layout - FSMs
FP Add FSM
Daily FSM
Feed Back FSM
Power FSM
Computation
FSM
Layout – Other Interesting Things
Is Zero Unit
Sense Amp Flip Flops
Register Enables
SRAM I/O and Sense-Amp
Layout – Whole Chip
Layout – Whole Chip
Verification Methodology
• Verilog Functionality
– “C” vs. Verilog
• Schematic Checks
– Schematic vs. Verilog
• Layout Verification
• Mode outputs
• FSM signals
• Power Gating
VDD Rise Verification
VDD Fall Verification
Final Output Verification
Issues Encountered
• Determination of distribution of work
between FPUs
• Routing of control signals
• Ground gating was not feasible
• Metal directionality problems
• FSM design issues
Sprinkler Buddy Specification
• Area
– 362um x 361 um
– 1:1.0001 Aspect Ratio
– .129 mm2 area
• Density
– .232 transistors / um2
• I/O
– 43 Inputs
– 2 Outputs
• Power
– Off State Power 2.4 mW
– With Standby 1.12 mW
Sprinkler Buddy
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Affordable, comprehensive, seamless
Low risk, high gain
Automated and low cost
Vast potential
Where do we go now ?
International Entry
Company Expansion
VC Investment
Beta Testing Period
Create System Prototype
End of
2007
Mid
2008
End of
2008
Mid
2009
Sprinkler Buddy Goes Global
India
South Asia
Asia
World