Transcript Document

E-Voting Machine
Final Presentation
• Group M1
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Bohyun Jessica Kim
Jonathan Chiang
Chi Ho Yoon
Donald Cober
• Design Manager
• Randal Hong
Wed, Dec 3
Secure Electronic Voting Terminal
Presentation Outline
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Marketing
Project Description
Behavior Description
Design Process
Floorplan
Schematics
Layout
Verification
Issues
Specification
Conclusion
Methods of Counting Ballots
• Early days, ballots were hand-counted
• Nowadays, voting machines were invented to
count votes more efficiently
• Major voting machines in market currently
• Optical Scan
• Direct Recording Electronic (DRE)
Optical Scan Machine
DRE Machine
Existing Systems and Falldowns
Optical Scan
• Scan marked paper
ballots and tally the result
• Cons:
• Voting system
configuration files
and removable media
• Exchange blank
ballot
• Expensive
DRE (Direct Recording Electronic)
• Records votes by means of a
ballot display which can be
activated by the voter
• Voting data stored in a
removable memory component
• In 2004, 28.9% of the registered
voters in the U.S. used DRE
system.
• Cons:
• Security of the DRE
software
• Expensive
Our Voting Machine
• It’s similar to DRE, but our unit does not store
any information
• Data is transmitted using 32-bit encryption
• Administrator initializes machine using
temporary key
• Increased speed
• Mainly it’s much cheaper!!!
Comparison
• $1.1 million to buy 200 optical scan voting machines at Centre
County, Bellefonte, PA
• Each DRE machine costs between $2500 and $3500
• Voter-verified paper ballot printer could add as much as $1000
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Touch screen
Fingerprint scanner
Printer
Id card reader
Our chip
Packaging
Manufacturing
Total unit price
$300
$40
$40
$20
$10
$45
$125
$600
Market Size
• 127883800 voters at 2008 Presidential Election
• Allegheny county, PA:
• 1321 polling places
• 956114 registered voters
• about 4500 voting machines
• About 159 people per machine
• For 2008 election total number of voting machines
estimated: 601892
• $600 * 601892 = $361135200 = $361million
Source: Pittsburgh tribune-review
Functional Overview
• Storing votes in a central machine but not in
local voting machines
• Integrated 32-bit TEA encryption
• Write-in ability
• Hard copy of vote
• Fingerprint scanner
• Simplicity
Key Features
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8-bit Databus
Compact design
FSM state encoders
Integer based TEA encryption
Behavioral Algorithm
Fingerprint
card
Key SRAM
ID SRAM
Choice SRAM
COMMs
User input
Message ROM
Display
Tx_check
Design Process
Overview
• Emphasis on low cost  small area
• C – Test encryption/decryption and monitored cycling of
8 cipher iterations.
• Verilog – Hardware implementation of each block in
FSMs and Comms.
• Floorplan - Addition of many flexible logic blocks and
buffers later significantly updated floorplan.
• Schematics – Updated as we ran the simulation and
debugged timing and transistor sizing errors.
• Layout – Updated as we ran extractedRC simulation
with reasonable load capacitances.
Design Process
C
Input Data: v = 0x12 34
• Used C to write encryption and
decryption Feistel cycles for
Comms Block using:
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16-bit blocks: Two 8-bit inputs
32-bit key: Four 8-bit keys
32 Feistel rounds = 16 cycles
• Wrote behavioral and structural
Verilog to mirror functionality of
C file.
Key = 0x77 8c ae 38
Iteration: 0x20 eb
Iteration: 0xc2 9c
Sum: 0xa00
Sum: 0x4600
Iteration: 0x7f c5
Iteration: 0xd0 6a
Sum: 0x1400
Sum: 0x3c00
Iteration: 0xf 6e
Iteration: 0x20 2a
Sum: 0x1e00
Sum: 0x3200
Iteration: 0xc5 73
Iteration: 0xc5 73
Sum: 0x2800
Sum: 0x2800
Iteration: 0x20 2a
Iteration: 0xf 6e
Sum: 0x3200
Sum: 0x1e00
Iteration: 0xd0 6a
Iteration: 0x7f c5
Sum: 0x3c00
Sum: 0x1400
Iteration: 0xc2 9c
Iteration: 0x20 eb
Sum: 0x4600
Sum: 0xa00
Iteration: 0xfd 58
Iteration: 0x12 34
Sum: 0x5000
Sum: 0x0
Encoded data = 0xfd 58 Decoded data = 0x12
34
Design Process
Verilog
• Verilog – Behavioral and structural implementation of
major blocks in FSMs and Comms. Comms: 3 total
design iterations as seen.
• All logic block changes written in Verilog first and
functionally tested before migrating to schematics.
• Floorplan modified in many stages due to concurrent
approach of adding small logics and re-simulating as
we passed LVS.
Design Process
Schematics
• Selected all standard cell parts keeping in mind low area
and power objective. Used many low power flip-flops to
drive FSM and Comms.
• Sized buffers for functionally correct rise/fall times and
propagation delay.
• Continuously simulated
and removed glitches before
moving to layout.
Design Process
Layout
• Used minimum wire width sizes for M3+M4 global and
databus interconnects.
• Specific M3, M4 wiring for Databus and interface
• Simulate and LVS’ed all large independent functional blocks before
global routing. For smaller logic we progressively added them to
full layout and passed LVS with simulation.
• Tried to maximize transistor density to achieve area and power goal.
Floorplan 1
COMMS
SRAMs
FSMs
● Initial floorplan
estimates for Comms
size was 4X smaller
than FSMs and SRAM
took half of chip real
estate
● Post-Verilog
● Heavy interconnects
over FSMs
● The address lines and
databus need to be
buffered
Floorplan 2
SRAMs
COMMS
● Second floorplan improved
major block size estimates.
Comms & FSMs ratio 1:1,
SRAM width shrunk
● Post-Schematics
● New aspect ratio 2:1
● 135 by 210
● Doubled size in COMMS
Block
FSMs
● The address lines and data
bus are buffered
Floorplan 3
● New aspect ratio 1:1
Key SRAM
● 147 by 132
● Post-layout
● Increased size in COMMS
● Decrease in FSM and SRAM
64 bit SRAM
Comms
FSMs
User_ID SRAM
Choice SRAM
● FSM connects to message
ROM, selection counter,
tx_check directly and SRAM
via databus
● Decoupled SRAM layout to fit
new layout
Floorplan 3.5
● Need to add key registers
and input buffer to Comms,
significantly increasing the
length. Flip Comms 90
degrees to accommodate
new length.
Floorplan 4
● 157 by 141
Key SRAM
● Aspect ratio lengthened
vertically slightly
KEY
REGISTERS
● Comms flipped 90 degrees
● Addition of integrated key
registers in Comms and input
buffer.
INPUT BUFFER
Random
Logic
Final Floorplan
● 157 by 141
● Aspect ratio lengthened
vertically slightly.
● Databus attached to FSMs,
SRAM, and Comms via
horizontal M4 layer.
SRAM
COMMS
Random
Logic
FSM
● Addition of random logic
such as TX-check, ROM,
User Input, Key SRAM,
changes the floorplan next to
FSMs.
Layout Process
• Flexible layout
design process
SRAM
• Important / Complex
blocks dictate the
overall layout
dimensions
• Design can be adapted
to significant changes
in major blocks
COMMs
SRAM
FSMs
SRAM
SRAM
Layout Process
SRAM
• Flexible design
process
• Not hindered by a stiff
floorplan
• Important / Complex
blocks can dictate their
own dimensions
• Design adapted to
significant changes in
major blocks
COMMs
SRAM
SRAM
SRAM
FSMs
Layout Process
• Innovative implementation strategy:
“Just put it somewhere”
Layout - SRAMs
64byte / 8byte / 4byte SRAMs
Density: .70
z
Layout - COMMs
COMMs
Size: 116 x 84 um
Density: .31
Layout - FSMs
FSMs
Size: 38 x 52 um
Density: .55
Layout – etc.
Layout CHIP
Final Design
Size: 157 x 141 um
Density: .39
Verification
You could just trust us….
Verification
• Time constraints will not allow us to run a full
chip simulation
So we need to show that our
4 main blocks:
•Logically simulate
COMMs
SRAMs
•Interact with correct
setup/hold/propagation timing
•Transmit signals with correctly
buffered strength
misc
FSMs
Logical Simulations -COMMs
COMMs
SRAMs
misc
FSMs
Testing Encryption
Timing
COMMs
SRAMs
misc
FSMs
Signal Strength
COMMs
SRAMs
misc
FSMs
Verification
COMMs
SRAMs
misc
FSMs
• Test cases
overlap in key
areas
• Combined
results
demonstrate
validity
Issues Encountered
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Buffering databus
Timing between state machines
Cadence update
Getting Spectre to work
Flip Flop glitching
Merging Cadence directories
Specifications
• Area
- 141 µm X 157µm
- Aspect Ratio of 1 : 1.113475
• Transistor Counts
- 9259
• Density
- 0.418 transistors/µm2
• Inputs/Outputs
- 24 inputs
- 16 outputs
- 16 I/O’s
E-voting Machine
Benefits
– Low cost and maintenance
– Simple and easy use
– Market availability
Upcoming dates…
– AMD Sponsored Presentation – Dec 3rd, 2008
– Meeting of the Minds – May 9th, 2009