Transcript Large-Scale SRAM Variability Characterization Chip in

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100
Itanium®
10
Xeon®
1
180 130 90 65
Technology Node (nm)
Effective SRAM Cell
Size (µm2)
On-Die L3 Cache Size
(MB)
Large-Scale SRAM Variability Characterization Chip
in 45nm CMOS
10
ITRS
Reported
1
0.1
300
30
Technology Node (nm)
High end microprocessors continue to require larger on-die cache memory
> 6σ of statistics needed to capture the variability of large cache memories
Problem: Getting statistics across large designs is $$ and difficult
Solution: Customized instrumentation on-chip
Large-Scale SRAM Variability Characterization Chip
in 45nm CMOS
Conventional Metrics – RSNM, IW, etc.
2.2mm×2.2mm
SRAM macros
 All-internal-node access
 360 CUTs per chip
 Limited silicon data
 Cannot correlate to cell bit fails in functional SRAM
Large-Scale SRAM Variability Characterization Chip
in 45nm CMOS
4×64Kb
SRAM Array
Switch Ctrl
4-Terminal
Switch Network
6-bit DAC
SENSE
FORCE
Large-Scale SRAM Metrics – SRRV, WWTV, etc.
2.2mm×2.2mm
Functional SRAM arrays
 Direct bit-line access
 768Kb per chip
 Silicon data measured for each SRAM cell
 Characterized under natural operating environment
 Correlate to cell bit fails in functional SRAM
Large-Scale SRAM Variability Characterization Chip
in 45nm CMOS
 The large-scale read/write margin measurements showed excellent correlation, near
failure, to SRAM DC RSNM and IW measurements
 µ/σ yield estimates has been shown to be highly dependent on the read stability or
writeability metric used and is therefore unsuitable for estimating yield
 Large-scale characterization of SRAM read stability and writeability is critical for SRAM
failure modeling and can be used to complement BIST and nano-probing
 Acknowledgement: NSF, C2S2, IBM Faculty Partnership Award, STMicroelectronics