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Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 3: Design Manager: Feb. 4th Steven Beigelmacher Size Estimates/Floorplan Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Status • Design Proposal (done) • Architecture (done) • High Level C Simulation • Behavioral Verilog & Test Bench • Final Algorithm & Major Functional Components • Floorplan & Structural Verilog (done) • Not yet simulated • To be done • • • • Gate Level Design Component Layout Chip Layout SPICE Simulation of Entire Chip Design Decisions (before) • Look-up tables and comparing values for look-up tables programmable. • 7 SRAM blocks (1 8x8, 2 8x1, 4 7x1) • Fixed point Multiplier for decimal numbers • Increment output register to know when multiplications are completed Design Decisions (after) • Look-up tables and comparing values for look-up tables programmable. • 2 SRAM blocks (1 8x10, 1 7x4) • Fixed point Multiplier for decimal numbers (same) • Increment output register to know when multiplications are completed (same) • Only one comparator is needed along with more control logic. SRAM Design • Writing to SRAM • Drive B and ~B with in and ~in • Assert select line • Value will be latched • Reading from SRAM • Assert precharge on positive edge • Assert select on negative edge • Low side will discharge through transistors to GND • High side will remain high • Transistor sizing • T3 must have larger resistance than T1 (narrower transistor) so value won’t be erased on read • Same for T4 and T2 SRAM Design • One 7x4 Block for Comparator Values – Sequential accesses for comparison (only 1 comparator) – Results stored in registers • One 8x10 Block for Look-Up Tables • All entries will be 12-bit entries – Done in bit slices for simplified interconnect Comparator Value Table Comp Value 0 1 2 3 4 5 6 speed load throttle oxygen 0 1 2 3 4 5 6 Bit Number 7 8 9 10 11 SRAM Layout 360 um Column Decoder R O W 48 um 8 x (10x12) Lookup Table D E C 144 um MUX 144 Decoder um Column 42 um R O W 7 x (4x12) Comparator Table D E C Individual Cell 6 um MUX 3 um Comparator Design For least significant bit: a0 a0 b0 a1 b1 a2 b2 a3 b3 a11 b11 a b For most significant bit: a11 a11 b11 a b Alternate Comparator Design Subtractor • 12 12 • vdd RC Adder Overflow sign • • Look at the sign bit to see which input is greater This design requires that your inputs and look-up table values be 2C encoded. Or it requires that you add a sign bit or do a conversion This would significantly change our design. Engine Speed 12bit Input Reg Manifold Pressure 12bit Input Reg before 7X1 L.U. Control Logic 8X8 SRAM Look-up 2:1Mux 2:1Mux 7X1 L.U. Fixed Point %Oxygen 12bit Input Reg 8X1 SRAM Look-up Array Multiplier 7X1 L.U. Throttle Position 12bit Input Reg 8X1 SRAM Look-up 12bit Output Shift Register OUTPUT 7X1 L.U. Engine Speed Manifold Pressure after 12bit Input Reg Control Logic 12bit Input Reg 7X4 SRAM Comparator Look-up 12bit Register 12bit Register %Oxygen Throttle Position 12bit Input Reg 12bit Input Reg 4:1Mux 2:1M ux =<> 3bit register Fixed Point Array Multiplier 8X10 SRAM Value Look-up 12bit Output Shift Register Floorplan • Basic Parts • • • • FA - 18µm X 11µm HA - 5µm X 7µm DFF - 21µm X 20µm Xor - 10µm X 7µm • These estimates are from downsizing 322 Fall 2002 layouts. Floorplan • Multiplier 144qndgqtes 11hq 11fq 11fq 210µm ……. ha 9FA ha 220µm Floorplan 7X4 SRAM 300µm Multiplier Comparator Registers and control logic 8X10 SRAM 400µm Total area: 120,000µm2 density: 0.13 trans/µm2 Metal Directionality Updated Transistor Count Registers (5 12-bit, shift) 2,568 SRAMS (1 8x10, 1 7x4) 6,720 Comparator 410 MUXs (2) 696 Control Logic 1,000 12-bit FP Multiplier 3,096 Decoders 1,000 TOTAL 15,490 difference -1,958 Problems • Figuring out how to optimize the comparisons • Optimizing the control logic Questions????