Transcript M - Washington State University

EE 466/586
VLSI Design
Partha Pande
School of EECS
Washington State University
[email protected]
Lecture 26
Semiconductor
Memories
Semiconductor Memory Classification
Read-Write Memory
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
Shift Register
CAM
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FLASH
Memory Timing: Definitions
Memory Architecture: Decoders
M bits
S0
S0
Word 0
S1
Word 1
S2
Word 2
SN 2 2
Nwords
SN 2
M bits
1
Storage
cell
Word 0
A0
Word 1
A1
Word 2
A K2
1
Word N 2 2
Word N 2 1
Decoder
Word N 2
Storage
cell
2
Word N 2 1
K 5 log2N
Input-Output
(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
Input-Output
(M bits)
Decoder reduces the number of select signals
K = log2N
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Hierarchical Decoders
Multi-stage implementation improves performance
•••
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
•••
NAND decoder using
2-input pre-decoders
A1 A0
A0
A1
A3 A2
A2
A3
Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
 DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
6-transistor CMOS SRAM Cell
WL
V DD
M5
M3
Q
Q
M1
b
M6
M4
M2
b
Wordline and Bitline
 Follow
board notes
CMOS SRAM Analysis (Read)
WL
V DD
M6
BL
M3
V DD
Cbit
Q
M1
Q
V DD
BL
M4
V DD
Cbit
Read Operation







Assume a “0” is stored on the left side of the cell, and a “1” on
the right side.
M1 is on and M2 is off.
The row selection line is raised to Vdd which turns on the access
transistors
Current begins to flow through M3 and M1to ground.
The resulting cell current slowly discharges the capacitance Cbit.
On the other side of the cell, voltage on b remains high since
there is no path to ground through M2.
The difference between b and b is fed to a sense amplifier
Read Operation

Current flowing through M3 and M1raises the output
voltage at node q which could turn on M2 and bring down
the voltage at node q
 It should not fall below VS
 Size M3 and M1appropriately.
 Make conductance of M13 to 4 times that of M3 so that the drain
voltage of M1does not rise above VTN

Cell discharge current
 Follow board notes
CMOS SRAM Analysis (Read)
1.2
Voltage Rise (V)
1
0.8
0.6
0.4
0.2
Voltage
rise [V]
0
0
0.5
1 1.2 1.5 2
Cell Ratio (CR)
2.5
3
CMOS SRAM Analysis (Write)
WL
V DD
M6
M4
Q
M3
Q
M1
BL = 1
V DD
BL = 0
Write Operation



The operation of writing 0 or 1 is accomplished by
forcing one bit line low while the other bit line remains
at about Vdd.
To write 1, b is forced low, and to write 0, b is forced
low
Conditions for writing 1
 Conductance of M4 is several times larger than M6 so that the
drain of M2 is pulled below VS.
 M1 turns off and its drain voltage rises to VDD due to the pull
up action of M5 and M3.
 M2 turns on and assists M4 in pulling output q to its intended
low value.
Write Operation




Size transistor pair M6 and M4
When the cell is first turned on for the write operation,
M6 and M4 form a pseudo-NMOS inverter.
Current flows through the two devices and lowers the
voltage at node q from its starting value of Vdd
The design of device sizes is based on pulling the
node below Vs
CMOS SRAM Analysis (Write)