Transcript Team 5

Access Control System
Final Presentation
EE 595 - Group 5
Access Control System
1
Team Member Introduction
and Expertise
JOHN BEAUCHAMP
MATT BRUNELL
Digital Design, PLD
VHDL Programming
Software, ADC,
DAC, concept-HDL
JEREMIAH BRYAR
NEGEDE BERHANU
PCB Layout Design
Power Systems, Power
Electronics
WILLIAM DIETRICH
HA VO
ADC, DAC,
concept-HDL, Law
AC/DC Motors
Access Control System
2
Non-Technical Description

To the user, an access control system is comprised of three
elements:
• A card or token (a.k.a., an identity credential)
• A door reader, which indicates whether the card is valid and entry is
authorized
• A door or gate, which is unlocked when entry is authorized

A user presents a card to a door reader, information from the
card is transmitted to the access control system, and the
system determines whether the card is valid and entry is
authorized. If the card passes, the system permits entry
into the door. If the card fails, the door remains locked.
Access Control System
3
Block
Diagram
Access Control System
4
Basic Operation of System
User Presents A Card
Card is Read by Card
Reader
Card Number is
Decoded and Sent to
Processor
Card Number is
Compared to Database
text
Does Card
Holder Have
Access to
Door?
No
Record Invalid Attempt
(Return to Top)
Yes
Open Door
Record Valid Attempt
(Return to Top)
Access Control System Basic Functional Diagram
Access Control System
5
Target Market by Geography
and Demographics

Offer product in the
U.S. and Canada (120
V @ 60 Hz).

Market to schools,
businesses,
apartment complexes

Product environment:
• access points to
structures
Access Control System
6
Business Case



The electronic access control
industry is estimated at $3.3
billion per year and is
expected to grow at 12.8%
annually.
Goal - sell 5,000 units in the
first year.
Less than 1% market share
initially expected.
Access Control System
7
Business Case (cont.)





Selling Price – $300
Material Cost – $60
Manufacturing Cost – $90
Development Cost – $900,000
Return on Investment – 15 months
Access Control System
8
Warning Labels
Access Control System
9
Capstone Project Role:
Assembly & Proto Mgr
Negede Berhanu
 BSEE
• Expertise:
 Design
• Block 1:
• Block 8:
Power, Power Electronics
Responsibilities
Power Supply
Relay Control
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10
Power Location Within Product
Level Block Diagram
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11
High Level Description of
Block





Converting 120 AC to 24 volt dc
 AC-DC converting transformer 120V,60Hz to
24 V dc.
Rectifier bridge
 A full waver rectifier bridge to decrease the
voltage ripple.
12V Voltage regulator
 Converting 24V to 12V
5V Voltage regulator
 Converting 24V-5V
A PNP Transistor to supply power to the SRAM
Access Control System
12
Performance Requirement

The micro processor



Super capacitor


Max voltage of 5.5
A battery charger



Max Voltage 5.5 min 4.2
max of a current of 100mA
Max voltage 13.8 min 11
Max 0.5A
The relay switch

Max voltage of 12.4V , Min voltage of 11.3V at Max
current of 1A
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13
Performance requirement
cont.


Mechanical interface soldered on PCB
board
In case on an accidental short it is
protected by fast acting fuse
Performance Requirment
Output Current Output Voltage Range
Voltage
Range
ripple, ΔV
Input VoltageRange
Part
MAX (V) MIN (V) MAX (A) MIN (A) MAX (V) MIN (V) Units V
12V regulator
40
15
3
0.5
11.4
12.6
0.01
5V regulator
40
8
3
0.5
5.25
4.75
0.01
Access Control System
Current
ripple, ΔI Delay
Units in mA
0.05
adj
0.05
adj
14
Standard Requirement




Operating temperature range 0-400C
 Testing for wide range of temperature for
shipping and storage
Operating Voltage and Frequency Range
 The operating voltage is 100-240 at
frequencies of 50/60Hz
Market geography
 North American market.
Safety
 Minimal concern for electric shock or hazard.
Access Control System
15
Standard Requirement

Allocation
Weight 70% of total weight
 PCB area 422.95 mm2; 1.65% of total
area


Cost 127,037;19.19% of total cost
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16
Block Diagram
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17
Theory of Operation
The ac to dc converter will change
the 120V to 24V
 The rectifier bridge will further
smoothen out the ripple on the 24V
signal
 The voltage regulator will change
the 24V to 12V and 5 V dc signal

Access Control System
18
Calculating The Bias on PNP
Voltage Drop Across VBE=.7
 Using voltage divider
Vb=Vs*R2/(R1+R2)=4
 Ve=VB-VBE=3.3V
 IB=VB-VBE/(RB+(β+1)Re)=.5μA

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19
Schematic
Access Control System
20
Simulation Result of
Rectifier Bridge
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21
Simulation Result of 12V and
5V Voltage regulator
Access Control System
22
Key Component Selection

12V and 5V
Switching regulator
• High Quality Factor
• High Reliability
• A wide rang of input
voltage
 15-40 12V
 8-40 5V
• Operating
Temperature of -55
to 105 degrees C
• Soldering 2350C for
5 sec
• Resistors:
 Constructed from
Metallic Film
 Low Cost
 Long lasting ability
 Temperature Coeff.
of Resistance -55 to
155 degree C
 Soldering t of 2350C
for 5 seconds
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23
Production BOM
QTY
Generic Name
Mfg 1
Mfg 1 Part #
10000
10000
10000
5000
5000
5000
10000
40000
20000
rectfir bridge
Diodes Inc.
HD04-T
Diodes Inc.
HD01-T
12 volts regulatorNational Semiconductor LM2576S-12
National Semiconductor
LM2576SX-12
5 volts regulator National Semiconductor LM2576S-5
National Semiconductor
LM340SX-13
transistor
Diode Inc.
MMBT4401T-7 Fairchild MMBT4401
resistors
Yageo America
9C12063A1000JLHFT
PanasonicERJ-8GEYJ101V
- ECG
resistors
Yageo America
9C12063A4020FKHFT
PanasonicERJ-14NF4020U
- ECG
diode
Fairchild Semiconductor BZX84C5V1
On semiconductor
1SMB5918BT3
capacitor
TDK Corporation
C4532X5R0J107M/3
AVX Corporation
NOJC107M004R
inductor
J W Miller Magnetics PM125S-101M Toko America
IRS122-5
Inc
Access Control System
Mfg 2
Mfg 2 Part #
24
Production BOM Cont
Place
Area
ment
TH/SMT Package
mm2
Auto/M
PCB
an
SMT
SMT
SMT
SMT
SMT
SMT
SMT
SMT
SMT
Totals
603
TO-263
TO-263
SOT-23
1206
1206
SOT-23
1812
603
auto
auto
auto
auto
auto
auto
auto
auto
auto
34.3
157.68
157.68
2.975
5.12
12.5
21.3
7.2
24.2
422.955
Function or
Description
full wave rectifier
Voltage regulation
Voltage regulation
Transistor
Resistor
Resistor
Diode
Capacitor
Inductor
Attributes Tol%
Operational
Operational
Operational
BJT
Operational
Operational
Operational
Zener
Operational
Totals
Access Control System
5%
5%
5%
5%
5%
5%
5%
5%
5%
$Cost/
$Cost Total
One
$0.20
$2.81
$2.81
$0.07
$0.01
$0.01
$0.03
$1.71
$1.37
$9.01
$2,000.00
$13,440.00
$13,440.00
$350.00
$25.00
$36.00
$346.00
$70,000.00
$27,400.00
$127,037.00
25
Statistics & Reliability:
λ, MBTF, R (t)
Generic Name
Mfg 1
Mfg 1 Part #
πv
π E π Q λ B(/10^9hr)λB(/years)
Rectfir Bridge
Diodes Inc.
HD04-T
0.053767993 1 1.25
12 volts regulator National Semiconductor
LM2576S-12
0.050672149 1 1.25
5 volts regulator National Semiconductor
LM2576S-5
0.050672149 1 1.25
transistor
Diode Inc.
MMBT4401T-7
0.123574744 1 1.25
resistors
Yageo America
9C12063A1000JLHFT 0.049787068 1 1.25
resistors
Yageo America
9C12063A4020FKHFT 0.069483451 1 1.25
Ziner diode
Fairchild Semiconductor
BZX84C5V1
0.032433241 1 1.25
capacitor
TDK Corporation
C4532X5R0J107M/3 0.098688241 1 1.25
inductor
J W Miller Magnetics
PM125S-101M
0.069483451 1 1.25
λ(year)
MTBF(year)
R(t)
1
8.8E-06
1.27613E-07
99.99994
1
8.8E-06
1.20266E-07
99.99994
1
8.8E-06
1.20266E-07
99.99994
5
4.4E-05
1.46647E-06
99.99927
0.7
6.1E-06
3.92642E-08
99.99998
0.7
6.1E-06
5.47976E-08
99.99997
3.2
2.8E-05
1.43349E-07
99.99993
2
1.8E-05
2.72614E-07
99.99986
1
8.8E-06
7.82823E-08
99.99996
2.42292E-06
412725.5122 99.99987
Total
 Total λ for the block, which is the sum of all λ is


2.422*10-6
Total MTBF=1/ λ
fit
412725.5122
The overall reliability of the block is
99.99987%
Access Control System
26
Statistics & Reliability:
Conclusion



The dominant part, transistor with
99.99927%.
The Zener diode we picked for this design
has the second lowest reliability at
99.99993%.
Picking more durable transistor at cost
tradeoff
Access Control System
27
Product Sustainability
Generic Name
Rectfir Bridge
12 volts regulator
5 volts regulator
transistor
resistors
resistors
Ziner diode
capacitor
inductor
Block 1 Product Sustainability
Primary Attribute Technology Attribute
Voltage
Technology Packaging
2.5σ
3.5σ
2.5σ
3.5σ
2.5σ 3.5σ
N/A
CMOS
CMOS
BIPOLAR
N/A
N/A
BIPOLAR
N/A
N/A
N/A
CC
CC
CC
1206
1206
CC
1812
603
N/A
2020.25
2020.2
2030.75
2020
2020
2030.75
2015
2010
N/A
2026.75
2026.75
2041.85
2032
2032
2041
2029
2020
N/A
2041.25
2041.25
2006.25
N/A
N/A
2041.85
N/A
N/A
Access Control System
N/A
2053.75
2053.75
2018.75
N/A
N/A
2018.75
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2006 2011.1
N/A
N/A
N/A
N/A
2006 2011.1
N/A
N/A
N/A
N/A
28
Product Sustainability
Prediction
Block 1 Product Sustainability
Generic Name
Rectfir Bridge
12 volts regulator
5 volts regulator
transistor
resistors
resistors
Ziner diode
capacitor
inductor
Technology Packaging
N/A
CMOS
CMOS
BIPOLAR
N/A
N/A
BIPOLAR
N/A
N/A
N/A
CC
CC
CC
1206
1206
CC
1812
603
2005 Prediction
Primary
Technology
Voltage
2.5σ 3.5σ 2.5σ 3.5σ 2.5σ 3.5σ
N/A
N/A N/A
N/A N/A
15.25 21.8 36.25 48.75 N/A
15.2 21.8 36.25 48.75 N/A
25.75 36.8 1.25 13.75 0.75
15
27
N/A
N/A N/A
15
27
N/A
N/A N/A
25.75 36 36.85 13.75 0.75
10
24
N/A
N/A N/A
5
15
N/A
N/A N/A
Access Control System
N/A
N/A
N/A
6.05
N/A
N/A
6.05
N/A
N/A
29
Obsolescence Analysis
The resistor will go obsolete by the
year 2015
 Since we have 10 year period no
change is recommended

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30
DFM Analog
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31
Block 8
Relay switch
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32
Relay Location Within Product
Level Block Diagram
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33
High Level Description of
Block


Relay switch
 A normally closed relay that will conduct
current through the coil in order to lock or
unlock a magnetic door lock
An inverter
 A digital inverter that will take a digital
signal form the microprocessor that will
late the relay operate as to the desired
operation (lock or unlock door)
Access Control System
34
Performance Requirement

A 12V inverter



Input voltage of 12.6-11.4V
A signal of 5V from microprocessor
The relay switch


Max voltage of 12.4V and Min voltage
of 11.3V
It will draw a Max current of 1A
Access Control System
35
Standard Requirement

Operating temperature range



Safety


The operating temperature range 0-420c
Testing for wide range of temperature for shipping and
storage
Since all of the component in going to be enclosed
within a the enclosure box there is a minimal concern
for electric shock or hazard.
Allocation


PCB Area 206.18mm2 ; 0.81% of total PCB area
Cost 81,990.00; 12.37% of total cost
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36
Block Diagram
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37
Design Theory



Relay is an electrically operated switch.
The relay will be used to energize or deenergize the magnetic lock that will open or
lock the door
The microprocessor will send a signal to the
relay
Access Control System
38
Implementation of The Design
Theory




The 12V dc attached to one end of relay
coil
The inverter will be powered by the 12V
at the other end of the relay coil
The input signal of the inverter will be
supplied by the microprocessor as high
being +5 and low being 0
Switching between 12V potential to 0V
Potential the relay will operate as desired
Access Control System
39
Production BOM
QTY
Generic Name Mfg 1
relay switch
10000 mosfet
10000
Omron Electronics
NEC
Mfg 1 Part #
Mfg 2
Mfg 2 Part #
G6BU-1114P-US-DC12 Omron Electronics,
G6CU-1117P-US-DC1
Inc-ECB Div
NE25139-T1
International Rectifier
IRLI2505
Access Control System
40
Production BOM Cont.
TH/SMT
Package
Placement Area
Function or
Attributes
2
Auto/Man mm PCB Description
TH Axial
auto
SMT SOT-143 auto
Total
198 relay switch
8.12 inverter
Tol% $Cost/One $Cost Total
Operational
MOSFET
206.12
Access Control System
$7.36
$0.83
$73,600.00
$8,300.00
$8.19
$81,900.00
41
Statistics & Reliability:
λ, MBTF, and Reliability
λ B (/109hr)
relay switch
mosfet
1 0.000008766
5 0.00004383
Total



λ B (/years)
λ(year)
MTBF(year)
R(t)%
7.82823E-08
99.99996086
5.00265E-07
5.78547E-07
99.99974987
99.99985536
1728467.679
Total λ for the block, which is the sum of all λ is
5.78547*10-7
Total MTBF=1/ λ fit 1728467.679
The overall reliability of the block is
99.99985%
Access Control System
42
Product Sustainability
Block 8 Product Sustainability
Primary Attribute Technology Attribute Voltage
Generic Name technology packaging 2.5σ
3.5σ
2.5σ
3.5σ 2.5σ 3.5σ
relay switch
mosfet
N/A
N/A
N/A
N/A
1990
1986
11.1
6.5
2017.75
2002.25
Access Control System
2028.9 2010 13
2008.8 2010 13
43
Product Sustainability
Prediction
Block 8 Product Sustainability
2005 Prediction
Primary Technology Voltage
Generic Name Technology Packaging 2.5σ 3.5σ 2.5σ 3.5σ 2.5σ 3.5σ
relay switch
mosfet
N/A
N/A
N/A
N/A
12.8 23.9 36.3 48.75 N/A N/A
2.75 3.75 35.3 48.75 N/A N/A
Access Control System
44
Obsolescence Analysis
The MOSFET will go obsolete by the
year 2009
 Due to a shorter period of time we
have before they go obsolete we
recommend using a newer version
inverter

Access Control System
45
Capstone Project Role:
Presentation Manager
Bill Dietrich
 BSEE
• Expertise: ADC, DAC, concept-HDL, Law
• Experience: UWM courses, Law
 Design
• Block 4:
Responsibilities
Input Conditioning Circuit
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46
Input Conditioning Circuit

Purpose
• The input conditioning circuit accepts a signal from
the card reader after a access card has been
scanned
• The circuit conditions the signal to ensure that
voltages, currents, and frequencies are within
permissible tolerances
• The circuit digitizes the signal using a Schmidt
Trigger
• The circuit passes the conditioned and digitized
signal through to Block 5 - PLD Parsing Circuit/PLD
Programming Interface
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47
Physical Block Location
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48
Board Level Schematic
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49
Interfaces
Signals
Signal Name
Door 1 - Data 0
Door 1 - Data 1
Door 2 - Data 0
Door 2 - Data 1
Block 4 Chart of Signals
Source
Card Reader
Card Reader
Card Reader
Card Reader
Destination
PLD
PLD
PLD
PLD
Two 5 V analog signals (per door)
Two conditioned 5 V digital signals (per door)
Physical
• All components in Block 4 are mounted on main
PCB board.
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50
Detailed Input Signal
Information
Input Signal generated by the Reader
and sent to the Input Conditioning
Circuit:

Governed by the Access Control
Standard Protocol for the 26-bit
Wiegand Reader.
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51
Logic Levels Coming From The
Card Reader
Voltage Levels
Data Outputs
(Data 1 and 0)
Min/Max
Voh
Vol
Ioh
Iol
4.0/5.5 V
0.0/1.0 V
0.0/1.0 mA
-25.0/0.0 mA
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52
Power Requirements

+5V supplied by Block 1
+5V +/- 5 %
 Max current consumption for Block 4
should be less than 100 mA

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53
Safety, EMC

Safety Concerns



Minimal risk of electric shock. Low current and
power components that are isolated from
user.
Infrared emission is negligible.
EMC


Digital IC’s need coupling capacitors and
should be grounded in an area specific to
digital components.
Any ESD should be avoided for IC’s.
Access Control System
54
Design Considerations

Transient Voltage
Suppressor (TVS)
protects against
undesirable voltage
swings from:
• induced lightning
• inductive load
switching
• electrostatic
discharge
Access Control System
55
Design Considerations

TVS operates
in the
avalanche
mode (a high
conductance
region)
Access Control System
56
Design Considerations

Positive
Temperature
Coefficient (PTC)
fuses are used to
protect
components from
overcurrent
conditions.
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57
Design Considerations

PTC operation:

When the rated threshold
current is reached, the
PTC begins to:
• Heat and
• Expand
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58
Design Considerations

PTC operation (cont.):


Expansion breaks carbon
paths inside the PTC and
resultantly reduces the
current through the
component
When the overcurrent
condition subsides, the
PTC cools and contracts,
the carbon paths are
restored, and current is
permitted to flow freely
again.
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59
Design Considerations

Inductor

Filters out high
frequency noise that
may damage or
interfere with the
operation of other
components
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60
Design Considerations

Resistors

Form a voltage divider
to regulate the supply
voltage given to the
Schmitt Trigger
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61
Design Considerations

The Schmitt Trigger


Performs a digitizing
operation by converting
an Analog input signal
to a Digital output
signal
Essentially acts as a
one-bit Analog to
Digital Converter
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62
Design Considerations

Power Ratings

Resistors – rated at 0.5 Watts

Inductor – rated at 0.7 Watts

Transient Voltage Suppressor – rated at
600 Watts (for instantaneous power)
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63
Design Considerations

Tolerances

Resistors – +/- 5% tolerance
• 1.0 kOhm resistor range – 950 to 1050 Ohms
• 10 kOhm resistor range – 9.5 to 10.5 kOhms

Inductor – +/- 10% tolerance
• 3900 uF inductor range – 3705 to 4095 uF
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64
Circuit Diagram for Design
Calculations
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65
Inductor Frequency Test
5.0V
2.5V
0V
0Hz
100KHz
V(PTC:2)
200KHz
300KHz
400KHz
500KHz
Frequency

After about 100 kHz, the inductor reduces the output voltage to
about 2 V.

Since the Schmitt Trigger has a minimum operating voltage of 2 V,
inductor effectively turns off the Schmitt Trigger.
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66
Design Calculations

Schmitt Trigger:
Has a min/max input of 2 V/5.5 V.
Therefore, voltage divider used to
reduce the input voltage:
VSch = 5 v (10 k / 1 k + 10 k)
VSch = 4.5 V
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67
Specific Device Parameters

Resistors:
• Constructed of Carbon Film
• Low Cost
• Exceptional Long Term Stability
• Temperature Coeff. of Resistance -55 to
155 degree C
• Solderability of 235 degrees C for 5
seconds
• Coated with tan colored laquer that is
resistance to solvents
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68
Specific Device Parameters

Inductor:
• Ferrite Magnetic Shielded
• Low Radiation
• High Quality Factor
• High Reliability
• Color Band Marking Identification
• Dielectric Strength of 1000 VRMS
• Operating Temperature of -55 to 105
degrees C
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69
Specific Device Parameters

PTC Fuse:
• Encapsulated, epoxy-coated body
• Solder-coated copper leads
• Operating Temperature of -55 to 125
degrees C
• Very Fast Acting
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70
Specific Device Parameters

Transient Voltage Suppressor:
• Void-free Transfer Molded Thermosetting
Epoxy Body
• Bidirectional over-voltage protection
• Operating Temperature of -65 to 150
degrees C
• Virtually instantaneous response time
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71
Special Manufacturing and
Testing

The TVS, PTC, resistors, inductor, and Schmitt
Trigger components:


Shall be tested to ensure they can withstand the upper
threshold voltages, currents, and power ratings as
advertised on the data sheet.
For instance, components could be tested by introducing
300 V to each components for 1 ms to ensure reliability.
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72
Special Manufacturing

All components are readily available
and of standard parameters.

At least three manufacturers
available for each component in the
Block.
Access Control System
73
Bill of Materials (BOM) for
single circuit
Bill of Materials
Item Number
Name
Designator(s)
Quantity
Item Cost
Extended Cost
1
1.0 KΩ Resistor
R1
8
$0.056
$0.45
2
10 KΩ Resistor
R2
8
$0.056
$0.45
3
3900 µF Inductor
L
8
$2.74
$21.92
4
PTC Fuse
Fuse
8
$3.83
$30.64
5
TVS
TVS
8
$0.70
$5.60
6
Schmitt Trigger Inverter
(hex)
Schmitt
8
$0.39
$3.12
7
Wiring, Solder
-
1
$0.25
$0.25
Sales Tax:
5.00%
Sub Total:
$62.43
Sales Tax:
$3.12
Final Cost:
$65.55
Access Control System
74
Manufacturing BOM
QTY
Generic Name
Mfg 1
Mfg 1 Part #
Mfg 2
Mfg 2 Part #
40,000
40,000
20,000
30,000
20,000
5,000
1.0 KΩ Resistor
10 KΩ Resistor
3900 µF Inductor
PTC Fuse
TVS
Schmitt Trigger Inverter
Yaego Co.
Yaego Co.
J.W. Miller
Littelfuse
Microsemi
Texas Instruments
CFR-25JB-1K0
CFR-25JB-10K
9250-395
0273.100H
P6KE7.5CA
SN74AHC14N
Panasonic - ECG
Panasonic - ECG
API Delevan
Cooper Bussmann
General Semiconductor
Fairchild Semiconductor
ERD-S2TJ102V
TH/SMT Package
TH
TH
TH
SMT
SMT
SMT
Axial
Axial
Axial
SMT
SMT
SMT
Placement Auto/Man
Area mm2 PCB
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
50
50
200
100
100
1600
Attributes
1/4 Watt
1/4 Watt
1/4 Watt
Very-Fast Acting
600 Watt
Chip has 6 individual inverters
2474-44L
BK/AGC-15/100
P6KE7.5CA
MM74HC14N
Function or Description
Reduces voltages and currents experienced by other components
Reduces voltages and currents experienced by other components
Protects components from exposure to very high frequencies
Protects components from exposure to very high currents
Protects components from exposure to very high voltages
Converts analog signals to digital
Tol% $Cost/One
$Cost Total
Asm PPM
Reli FITS
5%
5%
10%
N/A
N/A
N/A
$800.00
$800.00
$16,400.00
$83,700.00
$5,000.00
$1,462.50
998,100
999,680
998,100
999,960
998,600
967,020
18.2
18.2
2.0
3.1
2.6
9.9
$0.02
$0.02
$0.82
$2.79
$0.25
$0.29
Access Control System
75
Statistics & Reliability

Overall λ values for Block 4:
• Resistors: λ
• Inductor: λ
• PTC fuse: λ
• TVS: λ
• Schmitt: λ
• TOTAL
=
=
=
=
=
=
3.4x10-5
6.2x10-6
7.3x10-6
2.8x10-5
6.6x10-4
7.4x10-4
Access Control System
76
Statistics & Reliability: MTBF

Total MTBF :

MTBF = 1 / λ
FIT
• Total MTBF for Block 4
= 741 years
Access Control System
77
Product Sustainability
Predicted Component (IC) life parameters
Component
m + 2.5σ - p
m + 3.5σ - p
Obsolescence
Window
Applicable
Attributes
Resistors
2001.25
2009.75
( -3.75 , 4.75 )
None
Inductor
2010.00
2020.00
( 5.0 , 15.0 )
None
PTC
N/A
N/A
Unknown
None
TVS
2020.25
2026.75
( 15.25 , 21.75 )
Tech,
Package
Schmitt Trigger
2020.25
2026.75
( 25.75 , 36.85 )
Tech,
Package
Access Control System
78
Obsolescence Analysis
The resistors, inductors, and Schmitt trigger:
• Predicted to be the most obsolete parts according to the
calculations.
• No corrective actions are necessary since discrete
resistors and inductors will most likely be available much
longer than predicted.
Schmitt trigger also poses a possible
obsolescence problem, but:
• There are six (6) triggers per IC chip so there is some
redundancy, and
• There are at least 10 manufacturers of the component.
Access Control System
79
Personal Introduction
John Beauchamp
 BSEE,
• Expertise:
• Experience:
Guard
Digital Logic: PLD design
Avionics Technician, Wisconsin Air National
 Responsibilities
• Block 5 Design:
PLD Interface
• Capstone Project Role: Project Integrator
Access Control System
80
Task Estimates

Block Definition, System Design Phase




Approximately 40 man-hours
$0.0 material cost
Complete Phase completion date: 10/15/04
Detailed Design Phase



Approximately 75 man-hours
$46.00 material cost
Complete Phase completion date 11/5/04
Access Control System
81
Physical Block location



The Mach 4 PLD serves as an
interface between block 4 and
block 6, so it is located between
the two.
The oscillator is located right
next to the PLD so the clock
signal does not have to travel
excessive distances.
The DIP switch and seven
segment display are located in
the top left of the board for easy
access and viewing.
Access Control System
82
PLD Interface High Level
Description

Main Functions:


Convert two line digital
signal from card
reader/input signal
conditioning to a serial
digital signal to
microprocessor.
Decode a keypad button
press into a binary value
and serially transmit
decoded value to
microprocessor.
A key press
shorts a column
and a row
Access Control System
83
PLD Interface High Level
Description

Secondary functions -- Implemented in PLD to save parts
and board space.
 Provide selection of door egress and door status signals
 Display the binary board ID on a seven segment display
Access Control System
84
Performance Requirements


The PLD cycle time must be less then the minimum time that
the zeroline and oneline are held high so the PLD has time for
conversion and transmission.
Additionally, the frequency of the oscillator must be less than
the maximum speed of the PLD.
t
f
PLD Cycle
oscillator
= .27µs << t
INPUT HIGH
min = 20µs
= 3.7 MHz < f PLD max = 111.1 MHz
Access Control System
85
Performance Requirements


The length of the latch signal
to the PLD must be less than
the cycle time of the
microprocessor.
The maximum voltage from
the power supply must be
less than the maximum
source voltage rating of the
PLD.
tLATCH = .54 µ s > t
uP cycle
= .125 µs
Vpowermax = 5.3V < Vratedmax = 5.5V
Access Control System
86
Performance Requirements

The maximum current that the PLD can sink must be greater
than the current sourced when driving the seven segment
LED display.
Isinkmax = 8 mA > Idisplay = 5mA
Access Control System
87
ESD Considerations

The PLD is ESD sensitive, so a
warning sticker will be put on the
product enclosure.

If the equipment were available,
testing would be performed with
an electrostatic discharge gun.
Access Control System
88
Bill of Materials
QTY
5000
5000
5000
10000
Generic Name
Mfg 1
Mfg 1 Part #
3.6864MHz Clock Osc.
Mach 4 CPLD
4 position DIP switch
dual digit 7-seg display
Raltron
Lattice
Omron Elec.
Fairchild
Co1100
M4-64/32
A6T-4101
MAN3010A
$Cost/One
$0.47
$2.74
$1.17
$4.53
$Cost Total
$2,350.00
$1,370.00
$5,850.00
$22,650.00
Block 5’s total cost for one unit is $8.91.
Access Control System
89
Reliability Assessment Chart
Part
PPM
Reli
FITS
λB
πT
πV
πE
πQ
Overall
λ
Oscillator
57000
15
.00013
11.7
8
1.65
1
1.25
.0032
Mach 4
CPLD
16000
55
.00048
11.7
8
1.65
1
1.25
.0117
DIP
Switch
1000
5
.000043
11.7
8
.176
1
1.25
.000114
7
Segment
Display
4000
9
.000079
5.07
1.65
1
1.25
.000825
The overall block λ is .01584, and the overall MTBF is 63.14 years.
Access Control System
90
Obsolescence Chart
The table shows that the Mach 4 PLD and the Oscillator will be the first
components to go obsolete (6.15 years).
m s m+2.5s-p
Lattice Mach 4
Primary Attribute:
17.1
Secondary Attributes:
48.9
6.15
Device Type(PLD)
Technology(CMOS)
2001.0
2010.0
Process Voltage(5V)
1992.5
6.0
12.5
5.3
m+3.5s-p
11.1
36.4
0.85
Obsolescence window:
6.15)
Raltron CO01100(Oscillator)
Secondary Attributes:
6.15
9.4
(.85,
Process Voltage(5V)
1992.5
Package Type(DIP)
1987.0
5.3
7.8
0.85
1.6
Obsolescence window:
6.15)
(.85,
Lite-On LTD-2601B(7-seg. display)
Secondary Attributes:
Package Type(DIP)
9.4
Obsolescence window:
1987.0
Access Control System
7.8
1.6
(1.6, 9.4)
91
Component Selection –
Mach 4 PLD

PLD – Programmable Logic Device
 Logic implemented in device through schematic entry or
high level language, VHDL or Verilog.
 Memory is electrically erasable, meaning it can be
programmed and reprogrammed many times.
 Design consists of mixed VHDL modules and schematic
entry modules

32 I/O pins

External clock
Access Control System
92
Component Selection – PLD

Why use the Mach 4 PLD?


Saves board space when compared to using
7400 series TTL parts.
Minimal time delay – longest time delay
from input to output is 12 ns, regardless of
design.
Access Control System
93
Component Selection

Raltron 3.7 MHz Oscillator
• Stable frequency
• Low Cost

Fairchild Seven Segment
Display
• Available in common anode
configuration
• Nice Appearance
Access Control System
94
Block Diagram
PIC Microprocessor
Door1/Door2
Select Signals
Mux Out
2
Serial Comm.
4
Decoded
Keypad Serial
Communication
2
Mach 4 PLD
Door Status/
Door Egress Signals
7
Clock Signal
OSC
7
4
Keypad Decoding
Keypad
Reader 1 Code
Lines
2
2
4 position DIP switch
Reader 2 Code
Lines
Card Reader/Input Signal Conditioning
Access Control System
95
PLD Logic Schematic
Access Control System
96
Card Reader Code
Conversion

Two converter modules, one for each door

State machines implemented in VHDL

Each have oneline, zeroline and clk inputs and a serial
output and a latch signal for microprocessor
Access Control System
97
Converter Module State
Diagram

Starts in Idle state and
remains there until one
of the inputs go high

MaybeZero and
MaybeOne states exist to
prevent glitches and
allow setup time before
the latch

After the Latch output,
remains in wait state
until both line go zero
again
Access Control System
98
Converter Simulation
Results
Door Oneline goes
high
uP gets latch
uP latches low signal
Serial Out to uP
goes high
Access Control System
99
Keypad Decoder
16 bit counter
(VHDL)
Decimal to Binary
(VHDL)
2–4
demux
(VHDL)
Serial to Parallel
Shift Reg.
Output Control
(VHDL state machine)
Access Control System
100
Decoding Keypad

Columns A1, A2 and A3 are connected to a pull up
resistor and +5V

Rows Y0 through Y3 are connected to the outputs
of the 2-4 demultiplexor.

The two MSBs of the counter output are connected
to the input of the demux, causing one of the Y
rows to go low every fourth clock pulse.

If 5 on the keypad is pressed, this means that A2
and Y1 will be low every fourth clock pulse

All combinations of A1-A3 and Y0-Y2 are input to
OR gates.

The outputs of these OR gates are then input to an
active low decoder to get a binary value.
Access Control System
101
Serial Transmission of
Decoded Keypad Value



The rows A1-A3 are input to a NAND gate that.
The output of the NAND gate becomes high when any of A1-A3 become
low, indicating that a key has been pressed
The keyPressed signal starts the output control state machine and stops
the counter, freezing the keypad scanning.
Access Control System
102
State Diagram of Output
Control Module
Start = 1
Idle
Write
Setup
Write
Latch
Shift
Latch
Start = 0
Wait For
Depress







Latch
Shift
Latch
Shift
Stays in Idle until Start input becomes high
Write Setup state to allow the decoding to take place and sets the parallel
to serial shift register to write.
Write state clocks the register
First latch sets the register to shift and sends a latch signal to uP
Shift clocks the register, shifting the next bit to the output.
Continues until all data output and reach wait for depress.
Stays in wait for depress until start goes to zero, signaling that the key is
no longer pressed.
Access Control System
103
Keypad Decode Simulation
Access Control System
104
Current Progress

The PLD logic is entered to the chip correctly and
the PLD has correct computer simulations, but
no serial output is given to the microprocessor.

A likely reason for this is that the PLD is not
being clocked correctly by the oscillator.

Efforts will be made to give a better clock signal
to the PLD(ie: include a Schmitt trigger).
Access Control System
105
Personal Introduction
Jeremiah Bryar
 BSEE
• Expertise:
• Experience:
 Design
Digital Design, PCB layout, Troubleshooting
Internship – Security International, LLC
Responsibilities
• Block 6: Microprocessor Design Block
• Block 9: External Memory Design Block
• Capstone Project Role: PCB Layout Manager
Access Control System
106
Block 6 - Microprocessor

Purpose:
Provide control signals to implemented
board level functionality.
 Provide database functionality through
the external memory.
 Send serial communication TTL signals
from the processor to a RS-232 driver
for communication with an outside
computer.

Access Control System
107
Block 6 – Block Diagram
Access Control System
108
Block 6 - Microprocessor

Design:
 Microprocessor block receives parsed card reads,
multiplexed door egress, and multiplexed status switch
signals from the PLD.
 Holds firmware instructions and provides basic
resources for the running of those instructions.
 Provides the TTL signals that will be changed to RS-232
level signals when appropriate through the RS-232
driver chip.
 Controls the external memory block through firmware
driven address and data bus control.
Access Control System
109
Block 6 - Interfaces
Signals – All signals will be utilizing on-board traces on the
production PCB board and individual wires on the
prototype board. The serial communication will be
performed through a female DB-9 cable connector.
 Processor Input Signals
Signal Name
PLD0
PLD1
PLD2
PLD3
PLD4
PLD5
MuxSignal
Rx
D0
D1
D2
D3
D4
D5
D6
D7
Processor Input Signals
Transmitter
Reciever
PLD
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
Serial Buffer
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
Reciever Pin
Transmitter Pin
3
4
4
7
40
26
39
24
38
8
37
6
7
41
26
12
13/11
13/12
14/12
14/13
15/13
15/14
16/15
16/16
17/16
17/17
18/17
18/18
19/18
19/19
20/19
20/20
(xx/xx):(processor pin)/(SRAM pin)
Access Control System
110
Block 6 - Interfaces

Processor Output Signals
Signal Name
MuxControl0
MuxControl1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Tx
Relay0
Relay1
CE
WR
RD
Processor Output Signals
Transmitter
Reciever
Microprocessor
PLD
Microprocessor
PLD
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM Controller
Microprocessor
SRAM Controller
Microprocessor
Serial Buffer
Microprocessor
Relay Control Block
Microprocessor
Relay Control Block
Microprocessor
SRAM Controller
Microprocessor
SRAM
Microprocessor
SRAM
Reciever Pin
20
21
26
1
2
3
4
5
6
7
4
5
11
XX
XX
14
27
22
Access Control System
Transmitter Pin
5
6
36
35
34
33
30
29
28
27
24
23
25
21
22
10
9
8
111
Block 6 - Interfaces

Serial Input Signals
Signal Name
Txin
Rxin

Serial Input Signals
Transmitter
Reciever
Microprocessor
DB-9 Connector
DB-9 Connector
Microprocessor
Reciever Pin
3
26
Transmitter Pin
25
2
Reciever Pin
26
3
Transmitter Pin
2
25
Serial Output Signals
Signal Name
Txout
Rxout
Serial Output Signals
Transmitter
Reciever
DB-9 Connector
Microprocessor
Microprocessor
DB-9 Connector
Access Control System
112
Block 6 – Processor Signal
Level Definition








VIlow = (.2 * Vdd) = 1V
VIhigh = (.8 * Vdd) = 4V
VOlow = .6V
VOhigh = (Vdd - .7V) = 4.3V
IIlow = 8.0mA
IIhigh = -8.0mA
IOhigh = -1.3mA
IOlow =1.0mA
Access Control System
113
Block 6 – Power
Requirements

Block 6 requires a 5.0V source and a connection to
ground.


The tolerance for this input voltage is +/- .5V for all parts in
this block.
We planned for block 6 to need up to 100mA.




The maximum current the chip will draw in idle state with no
code running is 16mA at our input voltage and clock
frequency.
Maximum current consumption for the chip is 300mA if all
ports are sourcing their individual maximums.
The real consumption of the chip is highly dependent on the
firmware program running on the chip. As firmware fully
develops we will be measuring the true current consumption
of the chip.
The ST232ACN serial driver consumes between 1.5 and 4mA
for operation.
Access Control System
114
Block 6 – Safety, EMC

Safety Concerns



Minimal risk of electric shock.
Overall safety risk is minimal.
EMC Concerns



Digital IC’s need coupling capacitors & grounding in an area
specific to digital components.
Although the clock is not external to the IC, care should be
taken when working with clocked digital IC’s as the high
frequency clock signals could radiate over their respective
traces. In our particular case, this is not an issue because
trace length can be assumed to be zero.
As with all digital components care should be demonstrated
whenever handling a board. Handling should only be done
while following correct grounding procedure.
Access Control System
115
Block 6 Physical Location

Block 6 is located in the
center and far left of our
prototype board.

Block 6 is located center
and far right of our future
PCB board.
Access Control System
116
Schematic of Block 6
Access Control System
117
Theory of Design



The MCLR (low enable signal) could be affected by
transients introduced as initial start up of the board. In
order to minimize this, a resistor was tied to the MCLR pin
to minimize the input current that the processor could
receive.
Additional data lines were needed for communication with
the PLD. The total is 9, 6 for the card number transfer and
three for the multiplexed input door status and egress
signals.
Bypass capacitors were used to soften the voltage spikes
and dips as the board initially powers up.
Access Control System
118
Theory of Design
Continued



The PIC18F4620 does not automatically address external
memory, therefore the burden of external memory
operation lies heavily with firmware. We will be attempting
this as firmware matures.
We determined that it was in our best interests to create
the multiplexer internal to the PLD.
 This reduced the total number of IO pins used for
interfacing these signals by one and decreased our part
count also by one.
All components are DIP packages for ease of prototyping.
Access Control System
119
Theory of Design
Continued



The PIC chip sends a high signal to the door relay control
circuit to activate a relay to energize a door strike.
The PIC receives a high signal on the door status switch
which signifies that the door is closed. Otherwise the door
is open.
The PIC receives a high signal on the door egress switch
which signifies that the door should be unlocked for
opening.
Access Control System
120
Theory of Design
Continued



The PIC receives TTL level signals from the serial buffer.
The PIC sends TTL level signals to the serial buffer.
The RS-232 driver chip should be capable of
communication speeds greater than 100kbps. The
ST232ACN is capable of communication of up to 400kbps
at room temperature.
Access Control System
121
Tolerance Considerations
The bypass capacitors are not
greatly affected in their operation by
their tolerances.
 The current limiting resistor is not
greatly in it’s operation by either
extreme of it’s tolerances.

Access Control System
122
Experimental Evidence



The PIC chip has been successfully programmed and
simple programs have ran successfully in a laboratory
environment.
The serial communications works as outlined, we were
able to send data to the processor and have that data sent
back to the computer across a serial connection.
The processor has been able to activate the CE signals on
each of the SRAM devices, which is shown during our
start-up routine.
Access Control System
123
Special Manufacturing

There are no special manufacturing
consideration that need to be made
for this block. All parts can be easily
inserted into a PCB board by a pick
and place machine.
Access Control System
124
Production BOM for Block 6
Microprocessor Production BOM (Block 6)
Item Number
1
2
3
4
5
6
Name
ST232ACN
477-009-112-001
KT11B0CM
PIC18LF4620
05V10B103K or Generic
Generic
Sales Tax: 5.60%
Discription
RS-232 Buffer
Female DB-9 Adapter
Tactile Switch
8-bit Microcontroller
Tantalum Capacitor
Carbon Film Resistor
Designator(s) Quantity Item Cost Extended Cost
U2
1
$0.70
$0.70
J1
1
$1.70
$1.70
J2
1
$0.93
$0.93
U1
1
$7.07
$7.07
C1,C2,C3
3
$0.07
$0.21
R
1
$0.09
$0.09
Sub Total:
$10.70
Sales Tax:
$0.60
Final Cost:
$11.30
Access Control System
125
Capstone Project Role:
Project Integrator
Matt Brunell
 BSEE,
BSCS
• Expertise:
• Experience:
 Design
Software: C++,C,VB,
integrated circuits, concept-HDL
Hamilton Sundstrand CO-OP
(Defense Systems & Applied Research)
Responsibilities
• Block 7:
• PIC Firmware:
Enclosure Tamper prevention &
Keypad access
PIC18F4620 system firmware design,
implementation, testing, &
documentation
Access Control System
126
Physical Block Location




Critical Enclosure Tamper components will
be located on edge of PCB on the hinge
side of the enclosure
Keypad will be mounted on top lid of
enclosure.
Keypad pull up resistors located by PLD.
Schmitt trigger is located in block 4
Access Control System
127
Block 7 – Enclosure Tamper
Prevention & Keypad Access


Purpose:
 Provide level of security for access to hardware system
enclosure
 Signal system with enclosure access events
Design:
 After enclosure opens past a critical angle, the path
between an IR receiver & IR emitter will no longer be
blocked by an extension of the enclosure top.
 IR transmission results in a voltage drop at the
collector of a small transistor amplifier, which indicates
that the enclosure has been opened.
 User can enter access code with keypad to get
authorization to enter enclosure
 Keypad is scanned with PLD & code is sent serially to
PIC.
Access Control System
128
Block 7 - Interfaces
Signal

Input:
• Reflected IR beam
• Position of enclosure lid

Output
• ~1.5V - ~5.0V to schmitt trigger
• Schmitt trigger outputs 0V or 5V to PIC.

Physical


All parts mounted on main enclosure board.
10 digit keypad for user interface on top of
enclosure.
Access Control System
129
Block 7 –Power
Requirements

+5V power supply needed
+5V +/- 0.5 V
 Max current < 100 mA

Access Control System
130
Block 7 – Safety, EMC

Safety Concerns



Minimal risk of electric shock. Low power
devices.
IR emission is negligible, device will destroy
itself before harmful emission levels are
reached.
EMC


Digital IC’s need coupling capacitors &
grounded in an area specific to digital
components.
schmitt trigger robustness at 500V ESD.
Access Control System
131
Board Level Schematic
Enclosure access sensor schematic
Access Control System
132
Board Level Schematic
Keypad
scanning
schematic
- final design
implemented
in PLD
Access Control System
133
Top level Design

Top View into enclosure
Access Control System
134
Top level Design cont

Side View into enclosure
Access Control System
135
Top level Design cont

Keypad location:


Mounted on top panel of enclosure
Ribbon cable connection run to pin header by
the PLD
Access Control System
136
Design Considerations




IR emission at wavelength of 880nm.
IR drives base current of npn phototransistor in a common-emitter amplifier.
Amplified signal (0.8V – 5V) sent to
schmitt trigger and regulated to a
+5V/+0V logic level.
Exact thresholds for triggering need to
measured in lab to verify robustness of
operation.
Access Control System
137
Design Considerations

Transmitter/Receiver need to be directly
facing each other.

The gap between them will allow the
extension of the enclosure to pass freely
between them.

As enclosure opens, IR transmitter will no
longer be blocked.

Results in a logic high (5V) signal being sent
to the PIC.
Access Control System
138
Design Considerations
Max current for transmitter is
100mA
 After initial testing, power
consumption was analyzed and a
more efficient, yet still robust
current draw was established at
13mA( R1 = 330 ).

Access Control System
139
Design Considerations

Keypad will be scanned at 1/16 clock rate of the
PLD ~ 187 KHz.

Debouncing is critical. 5*R(2K)C(1uF) > 5ms

Length of access key determined to be 4 digits
long.

Last 4 digits count approach.

Output is 4 bit binary number.
Access Control System
140
Design Considerations

ALL necessary IC components for
keypad scanning can be created in the
PLD.



Lower part count / Part Costs
Lower manufacturing Costs
Higher system reliability
Access Control System
141
Design Calculations

Transmitter:
 V5v + VR1 + VTxled = 0 V
 5V - 4.4V - 0.6V = 0 V
 R1 = (4.4V) / (13mA) = 330 Ohm
Access Control System
142
Design Calculations

Receiver:

Enclosure Closed State:
•
•
•
•

V5v + Vce + VR2 = 0 V
IB effectively zero, transistor is shutoff
No current through R1
Output to schmitt trigger is ~ 5V
Enclosure Open State:
•
•
•
•
V5v + Vce + VR2 = 0 V
5V - VCEmin – R2*I = 0 V
5V – 4.2VCE – R2*I = 0 V
R2 = 0.8V / 1.6mA = 500 Ohms
Access Control System
143
Tolerance Considerations


Worst case tolerances
were set at 10% for
resistors. Beta of receiver
was varied from 150 to
350.
Worst case analysis:
 Most critical change
caused schmitt trigger
to receive 0.95 volts for
a low logic signal, which
is acceptable.
Access Control System
144
Special Manufacturing



LED’s will require lead
forming
LED emitter & LED receiver
will need a 90 degree bend
before insertion in to the
PCB.
Leads must place
transmission path 1.0 cm
above PCB.
Access Control System
145
Production BOM
QTY
Generic Name
Mfg 1
Mfg 1 Part #
5000
R1
Panasonic
5000
R2
Panasonic
15000
R3
Panasonic
ERD-S2TJ122V
ERD-S2TJ331V
ERD-S2TJ331V
5000
5000
5000
5000
5000
schmitt trigger-inverter
IR emitter
IR receiver
keypad
C1
Fairchild
Fairchild
Fairchild
grayhill
kemet
SN54AHC14
QSD-522
QSD-722
96ab-102-fl
05V10B103K
50
RB1
molex
10000
ribbon cripping socket
Hirose
5000
Ribbon Right Angle SMT
Hirose
82-22-5807
DF14-7S-1.25C
DF14-7S-1.25H
5000
5000
5000
15000
5000
Binary Counter
12 to 4 line priority encoder
3 to 8 decoder
Quad NOR gates
3 input Nand Gate
Fairchild
Texas Instruments
Fairchild
Texas Instruments
Texas Instruments
74AC163
IC0674HCMOS
74VHCT138A
SN54LV02A
SN74LV10ADBR
Access Control System
146
Production BOM Continued
Placeme
nt
TH/SMT Package
Auto/Ma
n
Area
mm2
PCB
Function or Description
Tol% $Cost/One
$Cost Total
TH
Radial
Auto
12
emitter-follower amp
5
0.0560
$280.00
TH
Radial
Auto
12
emitter-follower amp
5
0.0560
$280.00
TH
Radial
Auto
12
keypad scanning
5
0.0560
$840.00
SMT
TH
TH
TH
TH
SSOP
Axial
Axial
other
Axial
Auto
Auto
Auto
Auto
Auto
32
18
18
0
16
buffer for digital out
sends signal to Rx
drives amplifier with Tx
sends access code to pic
bypass capacitor
0
15%
15%
0
10%
0.2200
0.5700
0.4700
9.8500
0.0700
$1,100.00
$2,850.00
$2,350.00
$49,250.00
$350.00
x
other
Auto
0
connect keypad to PCB
0%
36.2800
$1,814.00
x
other
Auto
0
ribbon cable ends
0%
0.8000
$8,000.00
SMT
other
Auto
16
PCB ribbon cable connector
0%
0.9000
$4,500.00
SMT
SMT
SMT
SMT
SMT
SSOP
SSOP
SSOP
SSOP
SSOP
Auto
Auto
Auto
Auto
Auto
32
Keypad scanning incrementer
0
44
t ranslates selected key to binary output
0%
32 translates counter to Y matrix select0%
32 logic selection for selection matrix 0
32 trigger logic to indicate key pressed 0
0.4300
0.6100
0.4700
0.1700
0.1700
$2,150.00
$3,050.00
$2,350.00
$2,550.00
$850.00
Access Control System
147
Statistics & Reliability:
• Overall λ value for Block 7:
+
Resistors:
Schmitt:
IR Emitter:
IR Receiver:
Ceramic Cap:
Ribbon end:
Crimping socket:
Right Angle SMT:
Keypad:
TOTAL
λ
λ
λ
λ
λ
λ
λ
λ
λ
(5)
(0) – block 4
(1)
(1)
(1)
(2)
(1)
(1)
(1)
= 9.08*10-4
Access Control System
148
Statistics & Reliability:
MTBF & λfit
 MTBF

for total Block:
MTBF = 1 / λfit
• Total MTBF for Block 7 = 1/(9.08*10-4)
=

1100 years
Total λ fit = 103 failures per 109 hours
Access Control System
149
Statistics & Reliability:
Reliability of Block 7
Dominant part for Block 7:
keypad: reliability is the lowest at 99.81%



Excluding the schmitt trigger, the IR emitter has
the second lowest reliability at 99.96%.
Keypad reliability could be improved with a more
durable type.
IR reliability improvement with higher quality
part.
Access Control System
150
Personal Introduction
Jeremiah Bryar
 BSEE
• Expertise:
• Experience:
 Design
Digital Design, PCB layout, Troubleshooting
Internship – Security International, LLC
Responsibilities
• Block 6: Microprocessor Design Block
• Block 9: External Memory Design Block
• Capstone Project Role: PCB Layout Manager
Access Control System
151
Block 9 – External Memory


Purpose:
 Provide a medium for on-board data storage.
Design:
 Each memory location must be 8 bits wide.
 The parts should be 5V DIP parts for ease in
prototyping.
 We decided to use the CY62256 Dip package SRAM
Device for our project.
Access Control System
152
Block 9 – Block Diagram
Access Control System
153
Block 9 – External Memory
Signal Level Definition





VIlow = .8V (max)
VIhigh = 2.2V (min)
VOlow = .4V
VOhigh = 2.4V (min)
Vdrc = 2.0V (min)
Access Control System
154
Interfaces

Input Signals
Signal Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
WR
RD
CE
External Memory Input Signals
Transmitter
Reciever
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM (Address Bus)
Microprocessor
SRAM Controller
Microprocessor
SRAM Controller
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
Microprocessor
SRAM
Microprocessor
SRAM
Microprocessor
SRAM Controller
Reciever Pin
Transmitter Pin
26
36
1
35
2
34
3
33
4
30
5
29
6
28
7
27
4
24
5
23
13/11
13/12
14/12
14/13
15/13
15/14
16/15
16/16
17/16
17/17
18/17
18/18
19/18
19/19
20/19
20/20
27
9
22
8
14
10
(xx/xx):(processor pin)/(SRAM pin)
Access Control System
155
Block 9 - Interfaces

Output signals
 The External memory block outputs to the external
data bus when instructed to do so by the processor.
Signal Name
D0
D1
D2
D3
D4
D5
D6
D7
External Memory Output Signals
Transmitter
Reciever
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
SRAM (Data bus)
Microprocessor
Access Control System
Reciever Pin
13/11
14/12
15/13
16/15
17/16
18/17
19/18
20/19
Transmitter Pin
13/12
14/13
15/14
16/16
17/17
18/18
19/19
20/20
156
Block 9 – Power
Requirements

Block 6 requires a 5.0V source and a connection to
ground. Additionally, in this design the 5.0V source must
have support from the super-cap backup block.
 The tolerance for this input voltage is +/- .5V for
normal operation.
 Data retention for the SRAM guaranteed down to 2.0V.
 Data retention current consumption is 10uA max with a
nominal rating of 0.1uA.
Access Control System
157
Block 9 – Power
Requirements

We planned for block 9 to need up to 175mA.
 The SRAM controller consumes up to 50mA at full
operation and at full operation the SRAM device
consumes a maximum of 50mA and a minimum of
25mA when in idle non battery backup state. When in
battery backup state the SRAM device draws only about
.1uA (10uA max) of current nominally.
• We planned for 175mA because only one chip is
active at a time (50mA + 50mA +25mA + 25mA +
25mA = 175mA)
Access Control System
158
Block 9 – Safety, EMC


Safety Concerns
 Minimal risk of electric shock.
 Overall safety risk is minimal.
EMC Concerns
 Digital IC’s need coupling capacitors & grounding in an
area specific to digital components.
 The external memory is not robust to ESD so care
should be demonstrated whenever handling a board.
Handling should only be done while following correct
grounding procedure.
Access Control System
159
Block 9 Physical Location

Block 9 is located in the
center and far right of our
prototype board.

Block 9 is located center
and far upper right of our
future PCB board.
Access Control System
160
Schematic of Block 9
Access Control System
161
Theory of Design


The initial start up voltage of the system could fluctuate
significantly so bypass capacitors were tied between vcc
and ground of each device.
An LED was tied to the chip enable and to ground so that it
would illuminate when a particular chip is selected.
 The CE of each chip is also utilized sequentially as part
of the start-up routine. This shows that the program
has started on the processor and that the memory can
be selected.
Access Control System
162
Theory of Design



WR and RD was routed to each chip to facilitate the writing
and reading from the data bus.
The super-cap backup circuit has been tested and shown
to last for up to half an hour with a led tied directly to it,
further testing is necessary to determine how long the
SRAM will last off of those super capacitors.
A SRAM controller was selected to give the functionality of
a decoder with the additional functionality of on-board
battery backup in one chip.
 The batteries can not have a voltage higher than 4.0V
and the SRAM controller does not charge the batteries
necessitating the need for occasional maintenance in
the form of battery replacement.
Access Control System
163
Tolerance Considerations

The bypass capacitors are not greatly affected in their
intended application by their tolerances.
Access Control System
164
Special Manufacturing

There are no special manufacturing consideration that
need to be made for this block. All parts can be easily
inserted into a PCB board by a pick and place machine.
Access Control System
165
Production BOM for Block 9

The final production cost of this block is $15.70 with
applicable tax. This does not include the manufacturing
costs associated with building this block onto a PCB.
External Memory Production BOM (Block 9)
Item Number
1
2
3
4
Name
BQ2204
CY62256L-70PC
BH2430T-C
05V10B103K or Generic
Sales Tax: 5.60%
Discription
SRAM Controller
32k x 8 SRAM Device
24mm Battery Holder
Tantalum Capacitor
Designator(s) Quantity Item Cost Extended Cost
U3
1
$4.14
$4.14
U4, U5, U6, U7
4
$2.32
$9.28
J3, J4
2
$0.55
$1.10
C1,C2,C3
5
$0.07
$0.35
Sub Total:
$14.87
Sales Tax:
$0.83
Final Cost:
$15.70
Access Control System
166
Capstone Project Role:
Project Integrator
Matt Brunell
 BSEE,
BSCS
• Expertise:
• Experience:
 Design
Software: C++,C,VB,
integrated circuits, concept-HDL
Hamilton Sundstrand CO-OP
(Defense Systems & Applied Research)
Responsibilities
• Block 7:
• PIC Firmware:
Enclosure Tamper prevention &
Keypad access
PIC18F4620 system firmware design,
implementation, testing, &
documentation
Access Control System
167
PIC Firmware / GUI Development

PIC18F4620

MPLAB IDE
 MCC18 Compiler
 Development in C
PC Interface




RS-232 Serial Interface
Windows VT100
GUI developed in VB
with ActiveX
Access Control System
168
System Functional
Requirements

Translation from
performance
requirements to precise
statements

Removal of ambiguity in
system behaviors

Code Framework
Access Control System
169
Integrated Behavior Tree

Overall System Logic Flow
START
FR0
SYSTEM
[Conf Init]
FR0
FR0
SYSTEM
[Clock Setting]
FR0
SYSTEM
[Port Initialization]
FR0
SYSTEM
[Data Port Init]
FR0
FR0
SYSTEM
SYSTEM
<<Serial tx log>>
FR0
FR1
FR1
SYSTEM
[YES]
FR1
SYSTEM
??Boolian
Set=true??
SYSTEM
[YES]
FR1
FR1
SYSTEM
??Valid Card??
SYSTEM
[NO]
FR1
SYSTEM
[NO]
SYSTEM
[NO]
FR1
SYSTEM
??Egres s Sys tem??
FR2
VAR
>>Door# = <<
FE3
FR3
SYSTEM
??Boolian Set??
FR1
FR2
FR1
FR2
SYSTEM
FR2
TIMER
[Delay]
SYSTEM
[YES]
System
FR4
Sys tem
??Door Inclos er??
FR4
SYSTEM
??Enclos uer Aces s
Reques t??
SYSTEM
<<Key Pressed>>
FR3
SYSTEM
>>Door #=Sys tem
Door<<
FR4
SYSTEM
>>Key Code<<
FR3
SYSTEM
<<Door# [pin]=
High>>
FR4
SYSTEM
??Valid Key
Cycle??
SYSTEM
??event??
FR5
SYSTEM
??Inclosuer ??
FR5
SYSTEM
????
FR5
ENCl-SEC
[True]
FR5
MEMORY
>>Time Stamp
Valied<<
FR5
Encs-Sec
[False]
FR6
SYSTEM
??Ideal 10 Sec??
FR6
SLEEP
[SYSTEM-->Sleep]
FR7
SYSTEM
??Sleep??
FR7
SYSTEM
??Inputs??
FR7
FR8
SYSTEM
??Critical Votage??
FR9
SYSTEM
[Number Door
Timer]
FR8
SYSTEM
[sleep]
FR9
SYSTEM
[Reset]
SLEEP
[SYSTEM-->not
Sleep]
FR9
FR5
SYSTEM
[Inc Timer]
Memory
>>Time Stamp
Invalied<<
FR9
SYSTEM
[Action]
FR9
SYSTEM
??Event??
FR2
SYSTEM
[Delet]
FR1
FR1
SYSTEM
[FR3]
FR1
Temp Var
[Record timestamp
store in DB]
FR1
SYSTEM
[ADD Card]
FR2
FR1
SYSTEM
[Set
Boolian=fals e]
FR1
SYSTEM
[Return]
FR1
FR2
FR1
SYSTEM
[Return]
FR1
FR1
SYSTEM
??Valid Card??
SYSTEM
[YES]
SYSTEM
FR1
[Set
Boolian=t
rue]
FR1
FR1
FR1
FR1
FR1
FR1
SYSTEM
[Invoke time]
SYSTEM
[FR1]
SYSTEM
[FR2]
SYSTEM
<<time Stamp
Info>>
FR4
Key Code
??Valid??
FR4
KEY CODE
??Invalid??
FR3
MEMORY
>>time Stamp
Info<<
FR4
VARS
[Enclos uer
Acces s =True]
FR4
VAR
[Enclos er
Acces s =Fals e]
VAR
[Door# = -1]
FR3
SYSTEM
[Door# Status =0]
FR4
TIMER
????
FR4
Timer
????
FR3
TIMER
[Res et Door Timer]
SYSTEM
[Return]
FR2
FR1
FR3
SYSTEM
<<=Low>>
SYSTEM
[Set boolian=fals e]
SYSTEM
[House Keeping]
SYSTEM
[NO]
SYSTEM
[FR4]
SYSTEM
??User Card??
FR1
SYSTEM
[YES]
FR1
SYSTEM
??Valid Door??
FR1
SYSTEM
[YES]
FR1
SYSTEM
[FR5]
FR1
SYSTEM
[Open door]
FR1
SYSTEM
[Send Signal]
FR1
SYSTEM
[Start Timer]
FR1
SYSTEM
[Record
times tamp...]
FR1
SYSTEM
[Return]
FR1
SYSTEM
[NO]
FR1
SYSTEM
[Return]
Access Control System
170
Functional Testing


Firmware code Specialized to Verify
correct behavior of functional
requirements
Multiple types of test





Synchronization
Data verification
Environment response
Failure response
ATP for production level assembly
Access Control System
171
Regression Testing

Analysis of necessary testing after
any firmware change
Modular design of firmware functional
requirements ensure minimal
regression testing
 Revision changes must consider
compatibility with products already in
field.

Access Control System
172
GUI Interface Functionality

Initial Revision
Communication with Host PC through
windows hyper-terminal (VT100
emulation).
 Functionality:

• Set clock of the PIC
• Capture event log in text file
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173
GUI Interface Functionality

2nd Revision
User friendly GUI interface written in
VB.
 GUI uses batch command to control
VT100 transmissions
 Additional Functionality:

• Overall more user friendly
• capture current state of the system
• Capture or Display event log in window.
Access Control System
174
Phase 2 GUI Interface
Access Control System
175
GUI Interface Functionality

Production Revision





Stand-alone app
VT100 emulation done in-house with ActiveX
Windows Installer Implemented
Cross-platform compatibility
Additional Functionality:
• Real time monitoring of system
• Real System Control:
•
•
•
•
Enable/Disable doors for Security lockdowns
Enable/Disable users on the fly
Individual User history
Options to automatically email log file on schedule or
when specific events occur
Access Control System
176
Capstone Project Role:
Assembly & Proto Mgr
Ha Vo
 BSEE
• Expertise:
AC/DC Motors
 Design
Responsibilities
• Block 2:
• Block 3:
Battery Backup
Super Capacitor
Access Control System
177
Location of Blocks
Access Control System
178
High Level Description
Blocks 2 and 3
Access Control System
179
Performance Requirement Block-2
12v, Regulator
Battery
Input volt
range(V)
Input current
range(A)
Output volt
range(V)
Output current
range(A)
LM317
[12.0-12.5]
[0.5--3.0]
[12.0--12.5]
[0.4--0.5]
12V, 5A
[9.0—12.0]
[0.5--3.0]
[9.0--12.0]
[0.5--5.0]
Access Control System
180
BLOCK-2 DIAGRAM
Access Control System
181
Design Theory Block-2

We need the battery backup to provide 5A*h. At a
charging current of 0.5 (Amp) = (0.5*10 hours)= 5Amp

The charging current is limited by the small resistor (at
emitter of transistor).

Small R_5= 0.6V/( maximum charging current ) .
R_5 = 0.6V/(0.5A)= 1.2(Ω)

The charging voltage is controlled by potentiometer (5kΩ).
Access Control System
182
Block-2
Diagram of Charger
Access Control System
183
Key Component selection

Regulator LM317:
Supplying current charger [0.5Amp—
1.5Amp].
 Offering overload protection.


IC switch (LTC4412)
The IC is automatic switching between
DC sources.
 Offering reverse battery protection.

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Bill Of Material
• Resistor(220Ω):
•
•
•
•
•
•
•
•
•
•
$0.28
Resistor(100Ω):
$0.30
Resistor(1.2Ω):
$0.65
Potentiometer(5K): $0.40
Capacitor(0.1µF):
$0.75
Capacitor(2.2µF)
$0.75
Capacitor(100µF)
$0.94
Regulator:
$1.25
Diode:
$0.40
Transistor:
$0.75
IC:
$2.89
TOTAL
= $8.80
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Block-2
Total overall λ and MTBF



Total overall λ = 5.313E-3
Total MTBF
= 188.206
Time = 5 years
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Reliability For Block-2
•
•
•
•
•
•
•
•
•
•
•
Resistor(220Ω):
99.99911
Resistor(1.2Ω):
99.99911
Resistor(1.2Ω):
99.99911
Potentiometer(5K): 99.99906
Capacitor(0.1µF): 99.99906
Capacitor(2.2µF)
99.97209
Capacitor(100µF): 99.98401
Regulator:
99.98389
Diode:
99.99982
Transistor:
99.99966
IC:
99.95918
TOTAL
= 99.98792
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Sustainability For Block-2
Resistor-ERD-S2TJ101V
Resistor-ERD-S2TJ221V
Resistor-ERD-S2TJ1R2V
Capacitor-UVR1E101MED
Capacitor-2222 373 21225
Regulator-LM317T
Transistor
Primary attribute
Primary attribute
Primary attribute
Primary attribute
Primary attribute
Primary attribute
Secondary attribute
Third attribute
Primary attribute
Secondary attribute
Third attribute
resistance
resistance
resistance
capacitor
capacitor
Regualtor
PMOS
DIP
Amplifier
Bipolar
DIP
µ
σ
1980
1980
1980
1980
1995
2004
1968
1987
2004.5
1975
1987
8.5
14
8.5
14
10
6.5
8
7.8
8.3
12.5
7.8
2
. 5
σ
2001.25
2015
2001.25
2015
2020
2020.25
1988
2006.5
2025.25
2006.25
2006.5
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3
. 5
σ
2009.75
2029
2009.75
2029
2030
2026.75
1996
2014.3
2033.55
2018.75
2014.3
µ
+
2
. 5
σ
-3.75
10
-3.75
10
15
15.25
-17
1.5
20.25
1.25
1.5
- 2
0
0
5
µ
+
3
. 5
σ
- 2
0
0
4.75
24
4.75
24
25
21.75
-9
9.3
28.55
13.75
9.3
188
5
Block-2 testing
Charger & Battery
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Key Component selection

How does auto-switch(LTC4412) work:
• Vin (pin-1): This input is usually supplied power from a
battery or rectifier [-14V—36V]
• Sense(pin-6): This is output of IC chip [-14V—36V].
• Gate (pin-5): This pin uses to control back-up battery
that drives to load, when the rectifier is not presented.
• GND(pin-2) and CTL(pin-3) are connected to ground.
• The schottky diode is set to prevent reverse current.
• MOSFET works as a switch to control rectifier or backup
battery flow to load.
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Capstone Project Role:
Assembly & Proto Mgr
Ha Vo
 BSEE
• Expertise:
AC/DC Motors
 Design
Responsibilities
• Block 2:
• Block 3:
Battery Backup
Super Capacitor
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High Level Description Of Block-3
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BLOCK -3
SUPERCAP BACKUP
INPUT: 5Vdc from rectifier
OUTPUT: 5Vdc go to memory
The voltage input [5(V)—5.5(V)]
The current input [0.5(A)—3(A)]
The schottky diode is set to protect supercap.
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Bolck-3
Design requirement of Supercaps




Average Current Load: Iload= 20.01(µA)
Minimum Voltage:
Vmin= 3(V)
Maximum Voltage:
Vmax= 5.5(V)
Super-cap time: t (sec) = 259200(sec) = 3 days
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Block-3
DIAGRAM OF SUPERCAP
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Reliability For Block-3







Total overall λ = 1.0847E
Total MTBF
= 9218
Time
= 5 years
Capacitor(1.5F): 99.99792
Capacitor(1.5F): 99.9979
Diode:
99.96514
Total
= 99.98699
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Block-3
Bill Of Material
• Capacitor(3F):
• Diode:
• TOTAL
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$4.50
$0.40
= $4.90
197
Design Requirements Of Block-3




Capacitors store energy from rectifier (5v).
Capacitors work as battery when rectifier shuts
off.
How long do supercaps work to supply energy
for memory chips?
Schotky diode used to prevent reverse current
from capacitors to rectifier.
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Block-3
Design Theory And Equation








Working voltage: Vw
Minimum voltage: Vmin
Average discharge current: Iload
Discharge time in seconds: t(sec)
We can use the supercap about 3 days (259200(sec))
Energy need for discharge: E=(0.5)*Iload * (Vw + Vmin)*t
= 20.75(J)
Energy decrease in capacitor: E=(0.5)*C*((Vw)2 –
(Vmin)2) = 20(J)
The minimum capacitance value (F):
C = (Iload (Vw + Vmin)*t) / ((Vw)2 – (Vmin)2) = 2.5(F)
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Block-3
Lab Testing
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Questions?

Thank you.
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Appendix
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Costs and Part Count
Requirements











Total Part Count and Cost Per Block:
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 8
Block 9
Total =
–
–
Parts
Cost
$208,937
$25,650
$23,900
$108,162
$32,220
$57,496
$56,390
$81,900
$67,180
$661,835
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Product Assembly List
Identification and Documentation:
Product assembly 1 consists of the
main PCB that contains the
hardware for all blocks.
 Product assembly 2 consists of the
case with the attached keypad.

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Production Assembly
Component Procurement Setup
Determine quantities and source for mass
production.
Determine costs associated with procurement,
including shipping costs and any applicable
insurances.
Factor in component lead times.
Determine method for component storage and
location.
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Production Assembly
Substrate Fabrication
Outsource PCB layout & fabrication
 Determine lead time & shipping times
for fabrications

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Production Assembly

Fabrication, Component Preparation,
Baking and cleaning of the PCB Board





Prepare necessary parts.
Clean chlorides from PCB substrate.
Bake PCB substrate to eliminate excess
moisture.
Visual inspection of board for defects.
Possible x-ray for extensive defect inspection.
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Production Assembly

SMT package chosen for mass
production:
More reliable
 Low cost
 Smaller circuit board signature
 Easier to manufacture

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Production Assembly

Screen Solder Paste
Determine solder type & amount
 Determine screen pattern
 Determine angle and pressure for
application

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Production Assembly

Auto Component Placement
Calibrate automation machines
 Program automated machines for part
placement
 Determine assembly line configuration
for part flow


Vision System Inspection

Quality assurance inspection for
component placement
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Production Assembly

Reflow Solder
Determine oven temperature needed
for solder reflow
 Determine time PCB board spends in
oven


Vision/X-Ray System Inspection

Visual inspection to ensure quality of
component placement and integrity of
solder joints
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Production Assembly

Firmware Programming

In-circuit programming used to load
firmware after inspections
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Stress Testing
Initial Aging process used to
prematurely age product to about 3
months to make failures more
apparent.
Thermal stressing
 Vibration stressing
 Pressure stressing
 Overvoltage / Overcurrent stressing

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Package & Harnesses
Production and Tests
Finalized PCB is mated with the
case/keypad combination with
mounting hardware & ribbon cable.
 Additional stress testing will be
conducted.
 Final product is prepared for delivery
with automated packaging process.

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Product Sub-Assembly List
Identification and
Documentation:

Only Product assembly 1 includes a
PCB.
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Product Sub-Assembly cont.
Dimensions of sub-assembly 1,
the only PCB we use, are:
a maximum of:
12 inches in height
12 inches in length
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Product Sub-Assembly cont.
Key Component Layout on PCB:
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PCB Layout Dimensions










Block 1 - 1572 mm2
Block 2 - 1798.6 mm2
Block 3 - 129 mm2
Block 4 - 10,000 mm2
Block 5 - 5,000 mm2
Block 6 - 5,000 mm2
Block 7 - 215 mm2
Block 8 - 515.3 mm2
Block 9 - 1250 mm2
TOTAL AREA = 25,479 mm2
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Product Sub-Assembly cont.
Type of Substrate for PCB:

Rigid PCB.

Could use a flexible PCB, but
Product is not portable after
installation so not necessary.
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Product Sub-Assembly cont.
In Circuit Tests:
- Bed of nails test to verify correct
operation at board level.
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Product Sub-Assembly cont.
Functional Tests including IPC assembly
standards that are required:
- Fully automated test procedure to
ensure proper operation done through
software.
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