Transcript ppt - sm.luth.se

VLSI Design
SMD154
LOW-POWER DESIGN
Magnus Eriksson & Simon Olsson
1
Today’s Topics
•
•
•
•
•
Introduction
Power consumption
How to reduce power consumption
Tools used
In the future
2
Introduction
• Why do we want to decrease power
consumption?
– The marked wants longer battery life, higher
performance and smaller size for portable devices
– Small embedded systems with a small power source
that needs to have a long life time
– Lower power consumption decreases working
temperature of the device
3
Introduction
• Higher performance and longer battery life is
conflicting demands
– Sophisticated design techniques is needed to meet
both of them
• Power management is one of the most critical
design issues
– Meet the demands of the market
– Keep the working temperature at a acceptable level
4
Where is the power
consumed?
• Where is the power consumed?
– Static power consumption
– Short circuit power consumption
– Dynamic power consumption
Paverage  Pstatic  Pshort_ circiut  Pdynamic
Average power consumption
Static <1%
Short curcuit ~10%
Dynamic 90%
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Where is the power
consumed?
• Static power consumption
Vdd
Pstatic  VDD  I leakage
PULL-UP
NETWORK
in
out
PULL-DOWN
NETWORK
GND
GND
6
Where is the power
consumed?
• Short circuit power consumption
Vdd
Pshort_ circiut  VDD  I short_ circuit
PULL-UP
NETWORK
in
out
PULL-DOWN
NETWORK
Ishort_circuit
GND
GND
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Where is the power
consumed?
• Dynamic power consumption
Vdd
PULL-UP
NETWORK
1
2
Pdynamic     COUT  VDD  f
2
in
out
Switching
activity
Cout Switching
capacitance
PULL-DOWN
NETWORK
VDD Supply voltage
Idynamic
GND
ß
GND
f
Frequency
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Reducing dynamic power
consumption
• Decreasing switching activity (ß)
– Can be done by using specific algorithms and coding modes.
– This is the easiest way for a designer to influence the power
consumption.
• Decreasing switching capacitance (Cout)
– Can be done by using shorter wires and smaller devices.
– Can only be changed below gate level.
Pdynamic 
1
2
   COUT  VDD  f
2
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Reducing dynamic power
consumption
• Decreasing supply voltage (VDD)
– Has the biggest influence on dynamic power consumption.
– Lower supply voltage results bigger delays.
– The critical path must be reduced to make a lower supply
voltage possible.
• Decreasing frequency (f)
– Will reduce the performance.
– Performance and power consumption must be balanced.
Pdynamic 
1
2
   COUT  VDD  f
2
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Decreasing switching
activity
• Different coding techniques
– Fewer bit transitions between two states
• Boolean expressions simplification
– Gate minimization
• Avoid glitches
– Get rid off unnecessary transitions
• Power down modes
– Turn off parts of that are not in use
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Different coding techniques
• Gray coding
– Hamming distance of one
– Used when a sequence is
predictable
• FSMs
• Address busses
– Makes full use of the
bit-width
100
000
001
101
111
011
110
010
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Different coding techniques
• Bus-inversion coding (BI)
– Compare the previous and current word
– Invert the data if it results in fewer transitions
– A flag bit is used with the bus to indicate if the
data is inverted or not
– Suited for data busses
• Partial bus-inversion (PBI)
– Divides the bus in different parts with its own flag
– Suited for address busses
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Different coding techniques
• Sign magnitude
– Uses only one bit for the sign in contrast too two’s
complement
– Result in fewer transitions when going from a
positive to a negative number
– Needs more logic to implement than two’s
complement
sign
bn bn-1
magnitude
...
b0
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Boolean expressions
simplification
• Minimize the number of gates to avoid
unnecessary transitions
• Just minimize the number of gates is not
optimal if the activity of the signals differ
– One example
• Both expressions have the same number of gates
• If A have the highest transition activity Y is the better
solution (A only affects two gates instead of three)
X = AB + AC + CD
Y = A(B + C) + CD
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Avoid glitches
• Glitches results in unnecessary transitions,
glitching power loss
• Logic with a long depth are more prone to have
glitches
• Flip-flops can be added to shorten the depth
of the logic to minimize the influence of
glitches
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Power down modes
• Power supply shut down
– Turns of the power in an entire module
– Reducing the power consumption in that part to
zero
• Clock gating
– Halts the clock signal and reduces dynamic power
consumption to zero
– There will still be leakage
– Gating the clock will increase the clock skew
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Power down modes
• Memory partitioning
– Shut down a part of the memory that is not used,
no information is stored at the moment
– Some method to know when a partition is used is
needed
– Memory usage spread out over several partitions
can be a problem
• Flip-flop enable
– Decreases switching activity of flip-flops that are
disabled but the clock signal is still active at all the
time
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Tools
• Two major categories
– Power-analysis/estimation
• Estimates what parts of the design that will consume most
power
• Lets the designer do high level optimizations in an early
stage
– Power-optimization
• Implements different power optimization techniques
• Can be done without the interaction of the designer
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Tools
• Used on different levels of the design
– Behavior-level
• Not implemented in any commercial tools
– RT-level
• Fast power estimations can be done due to the high
abstraction level
• Clock gating can be implemented as a power optimization at
this level
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Tools
• Used on different levels of the design (cont.)
– Gate-level
• The power consumption can be estimated from the
equation for dynamic power consumption
• Medium accuracy and speed
– Transistor-level
• The result is very accurate both for power estimation and
optimization
• Tools used at this level are not very popular due to; high
runtime and that most vendors do not provide transistor
level netlists
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Tools
• Cadence Encounter
– Supports power
optimizations, e.g.
• Clock gating
• Multi-supply voltage
(voltage scaling)
– See figure for
complete low-power
design flow
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Tools
• Synopsys power compiler
– Used both for power analysis and power
optimization
– Power analysis can be done both on RT- and gatelevel
– Power optimizations that can be done are
•
•
•
•
Clock gating
Operand isolation
Leakage optimization
Etc.
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The future
• To meet the demands of higher performance
and longer battery time new techniques are
needed
• Leakage will be a bigger part of the total
power consumption when smaller technologies
are used
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