Transcript Q=1
Review: Basic Building Blocks Datapath Execution units - Adder, multiplier, divider, shifter, etc. Control Finite state machines (PLA, ROM, random logic) Interconnect Register file and pipeline registers Multiplexers, decoders Switches, arbiters, buses Memory Caches (SRAMs), TLBs, DRAMs, buffers Review: Read-Write Memories (RAMs) Static – SRAM data is stored as long as supply is applied large cells (6 fets/cell) – so fewer bits/chip fast – so used where speed is important (e.g., caches) differential outputs (output BL and !BL) use sense amps for performance compatible with CMOS technology Dynamic – DRAM periodic refresh required small cells (1 to 3 fets/cell) – so more bits/chip slower – so used for main memories single ended output (output BL only) need sense amps for correct operation not typically compatible with CMOS technology Review: 4x4 SRAM Memory 2 bit words read precharge enable bit line precharge WL[0] !BL BL A1 WL[1] A2 WL[2] WL[3] clocking and control A0 Column Decoder sense amplifiers BL[i] BL[I+1] write circuitry 6-transistor SRAM Cell WL M2 M5 M6 !Q M1 !BL M4 Q M3 BL SRAM Cell Analysis (Read) WL=1 M4 M5!Q=0 M6 Q=1 M1 Cbit Cbit !BL=1 BL=1 Read-disturb (read-upset): must carefully limit the allowed voltage rise on !Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints SRAM Cell Analysis (Read) WL=1 M4 M5!Q=0 M6 Q=1 M1 Cbit Cbit !BL=1 BL=1 Cell Ratio (CR) = (WM1/LM1)/(WM5/LM5) V!Q = [(Vdd - VTn)(1 + CR (CR(1 + CR))]/(1 + CR) Read Voltages Ratios Vdd = 2.5V VTn = 0.5V 1.2 Voltage Rise on !Q 1 0.8 0.6 0.4 0.2 0 0.3 0.6 0.9 1.2 1.5 Cell Ratio (CR) 1.8 2.1 2.4 SRAM Cell Analysis (Write) WL=1 M4 M5!Q=0 Q=1 M6 M1 !BL=1 BL=0 Pullup Ratio (PR) = (WM4/LM4)/(WM6/LM6) VQ = (Vdd - VTn) ((Vdd – VTn)2 – (p/n)(PR)((Vdd – VTn - VTp)2) Write Voltages Ratios Vdd = 2.5V |VTp| = 0.5V p/n = 0.5 1 Write Voltage (VQ) 0.8 0.6 0.4 0.2 0 0.3 0.6 0.9 1.2 1.5 Pullup Ratio (PR) 1.8 2.1 2.4 Cell Sizing Keeping cell size minimized is critical for large caches Minimum sized pull down fets (M1 and M3) Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle Minimum width and length pass transistors Boost the width of the pull downs (M1 and M3) Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger 6T-SRAM Layout VDD M2 M4 Q Q M1 M3 GND M5 BL M6 BL WL Multiple Read/Write Port Cell WL2 WL1 M2 M5 !Q M4 Q M7 M8 M1 !BL2 !BL1 M6 M3 BL1 BL2 4x4 DRAM Memory 2 bit words read precharge enable bit line precharge WL[0] BL A1 WL[1] A2 WL[2] WL[3] sense amplifiers clocking, control, and refresh BL[0] BL[1] A0 BL[2] BL[3] Column Decoder write circuitry 3-Transistor DRAM Cell WWL WWL RWL write Vdd M3 M1 X BL1 M2 Cs X Vdd-Vt RWL read BL2 BL1 Vdd-Vt BL2 No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a “1” is VWWL - Vtn V 3T-DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 1-Transistor DRAM Cell WL WL M1 Cs CBL BL write “1” read “1” X X BL Vdd/2 Vdd-Vt Vdd sensing Write: Cs is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between CBL and Cs Read is destructive, so must refresh after read 1-T DRAM Cell Capacitor Metal word line M1 word line SiO2 poly n+ Field Oxide n+ poly Inversion layer induced by plate bias Diffused bit line Polysilicon Polysilicon plate gate (a) Cross-section (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area DRAM Cell Observations DRAM memory cells are single ended (complicates the design of the sense amp) 1T cell requires a sense amp for each bit line due to charge redistribution read 1T cell read is destructive; refresh must follow to restore data 1T cell requires an extra capacitor that must be explicitly included in the design A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than Vdd)