Transcript Slide 1

Design and Implementation of VLSI Systems
(EN0160)
Lecture 18: Static Combinational Circuit Design (2/2)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
Last lecture
• Conversion of AND/OR circuits to NAND/NOR/INV circuits.
• An asymmetric gate favor one input over the other(s).
• A skewed gate favor one transition over the other(s).
S. Reda EN160 SP’07
What is the P/N ratio that gives the least
delay?
• We have selected P/N ratio for unit rise and fall resistance (m = 2-3
for an inverter).
• Alternative: choose ratio for least average delay
• By sacrificing rise delay, pMOS transistors can be downsized to
reduced input capacitance, average delay, and total area
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pMOS is the enemy!
B
4
A
4
Y
1
1
• pMOS is the enemy!
– High input and diffusion capacitance for a given current
• Can we take the pMOS capacitance off the input?
• Various circuit families try to do this…
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Let’s get rid of pMOS
 Reduced the capacitance and improved the delay
 Increased static power consumption
How can we implement the R easily in a CMOS process?
[see subsection 2.5.4]
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1. Pseudo-nMOS circuits
• In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
• In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of pulldown network
[see subsection 2.5.4]
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Logical effort of pseudo-nMOS gates
• Design for unit current on output to compare with unit inverter.
• pMOS fights nMOS
logical effort independent of
number of inputs!
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Pseudo-nMOS power
en
Y
A
B
C
• Pseudo-nMOS draws power whenever Y = 0
– Called static power P = I•VDD
– A few mA / gate * 1M gates would be a problem
– This is why nMOS went extinct!
• Use pseudo-nMOS sparingly for wide NORs
• Turn off pMOS when not in use
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Ganged CMOS
Traditional pseudo-nMOS
• When A=B=0:
• both pMOS turn on in parallel pulling the output high fast
• When both inputs are ‘1’:
• both pMOS transistors turn off saving power over psuedo-nMOS
• When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case
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2. Cascode Voltage Switch Logic (CVSL)
• Seeks the performance of pseudo-nMOS without the static power
consumption
• CVSL disadvantages:
– Require input complement
– NAND gate structures can be tall and slow
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3. Pass Transistor Logic
B
A
B
F = AB
0
Advantage:
• just uses two transistors
Problem:
• ‘1’ is not passed perfectly
• cannot the output to the input of another gate
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Complementary Pass Transistor Logic (CPTL)
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=A
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
F=A
EXOR/NEXOR
• Complementary data inputs and outputs are available
• Very suitable for XOR realization (compare to traditional CMOS)
• Interconnect overhead to route the signal and its complement
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Possible solution: interface to a CMOS inverter
3.0
In
In
VDD
Voltage [V]
1.5mm/0.25mm
x
Out
0.5mm/0.25mm
0.5mm/0.25mm
2.0
Out
x
1.0
0.00
0.5
1
1.5
2
Time [ns]
Threshold voltage loss causes static power consumption
V DD
V DD
Level Restorer
Mr
B
A
Mn
M2
X
Out
(AKA Lean Integration
with Pass Transistors
- LEAP)
M1
A better design: full swing; reduces static power
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Pass Transistor Logic with transmission gates
• In pass-transistor circuits, inputs are also applied to the
source/drain terminals.
• Circuits are built using transmission gates.
Problem:
• Non-restoring logic.
• Traditional CMOS “rejuvenates” signals
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Restoring Pass Transistor Logic
S
A
VDD
M2
F
S
M1
B
S
Next time: Dynamic circuits
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