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Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3 Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’07 Project update • Phase I: Turn your standard cells to Mike today. Mike will iterate with you for the next couple of days and distribute the library file/report on Wednesday April 11. • Phase 2: Write precisely the interface (input/output) of your module in the CPU and write in plain english or pseudo-code what your module should do/output for different input combinations. Turn this in to Brian by Monday (April 16). Brian will verify everything and distribute the report on April 18. S. Reda EN160 SP’07 Answer to a FAQ on the standard cell DRC • Why do we get the “not enough metal density” DRC warning? • CMP (chemical mechanical Wafer carrier polishing) is executed for each layer before buildup of Wafer other layers Rotating platen • How can metal fill insertion helps in smoothing surfaces? Area fill features Post-CMP ILD thickness S. Reda EN160 SP’07 Downforce Polishing pad Slurry dispenser Polishing slurry Adders • Addition is the most commonly used arithmetic operation • It is often the speed limiting element • Careful optimization of the adder is of the utmost importance • Optimization can be carried out at the circuit or logic level S. Reda EN160 SP’07 Half and full adder S. Reda EN160 SP’07 A N-bit adder can be constructed by cascading 1-bit FA A0 B0 Ci,0 A1 B1 Co,0 FA A2 B2 Co,1 A3 B3 Co,2 Co,3 FA FA FA S1 S2 S3 (= Ci,1) S0 Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit S. Reda EN160 SP’07 Full adder Boolean equations A Cin B Full adder Cout Sum S A B C Cout MAJ ( A, B, C ) S. Reda EN160 SP’07 S = A B Ci = ABC i + ABC i + ABCi + ABCi C o = AB + BC i + ACi An implementation that requires 28 transistors VDD VDD A Ci A B B A B B Ci A X Ci VDD Ci S A Ci A B B VDD A Co S. Reda EN160 SP’07 B Ci A B Problems with the design VDD VDD A Ci A B B A B B Ci A X Ci VDD Ci S A Ci A B B VDD A Co Cons B Ci A B Nevertheless • Large area • Ci is connected to the transistor • Tall transistor stacks closest to the output • Large intrinsic capacitance for Co S. Reda EN160 SP’07 Inversion (self-dual property) A Ci A B FA S Co Ci B FA S S A B C i = S A B Ci C A B C = C A B C o i o i S. Reda EN160 SP’07 Co Minimize critical path (carry) by reducing the number of inverters Even cell A0 Ci,0 B0 , FA S0 A1 Co,0 B1 , FA S1 A2 Co,1 Odd cell B2 , FA A3 Co,2 S2 • FA’ does not have an output inverter S. Reda EN160 SP’07 B3 , FA S3 Co,3 Can we do better? PGK design • For a full adder, define what happens to carry – Generate: Cout = 1 independent of C • G=A•B – Propagate: Cout = C • P=AB – Kill: Cout = 0 independent of C • K = ~A • ~B S. Reda EN160 SP’07 The mirror adder VDD VDD A B VDD A B B Ci A B Kill "0"-Propagate A Ci Co Ci S Ci A "1"-Propagate Generate A B B A B Ci A B 24 transistors S. Reda EN160 SP’07 Mirror adder stick diagram VDD A B Ci B A Ci Co S GND S. Reda EN160 SP’07 Co Ci A B