Transcript lecture13 - Brown University

Design and Implementation of VLSI Systems
(EN0160)
Lecture 13: Power Dissipation
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
Power and Energy
• Power is drawn from a voltage source
attached to the VDD pin(s) of a chip.
• Instantaneous Power: P(t )  iDD (t )VDD
• Energy:
• Average Power:
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T
T
0
0
E   P(t )dt   iDD (t )VDDdt
T
E 1
Pavg    iDD (t )VDD dt
T T 0
Dynamic power
• Dynamic power is required to charge and discharge
load capacitances when transistors switch.
•
•
•
•
One cycle involves a rising and falling output.
On rising output, charge Q = CVDD is required
On falling output, charge is dumped to GND
VDD
This repeats Tfsw times
iDD(t)
over an interval of T
fsw
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C
Dynamic power dissipation
Vdd
Vin
Vout
CL
load capacitance
(gate + diffusion +
interconnects)
Energy delivered by the supply during input 1  0 transition:
Energy stored at the capacitor at the end of 1  0 transition:
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dissipated in NMOS
during discharge
(input: 0  1)
Capacitive dynamic power
 If the gate is switched on and off f01 (switching factor) times
per second, the power consumption is given by
 For entire circuit
where αi is activity factor [0..0.5] in comparison to the clock
frequency (which has switching factor of 1)
Pdynamic  CVDD 2 f
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Short circuit current
• When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are
comparable for input and output
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Dynamic power breakup
Gate
34%
Interconnect
51%
Diffusion
15%
Total dynamic Power
[source: Intel’03]
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Calculating dynamic power: An example
• 200 Mtransistor chip (1.2 V 100 nm process Cg = 2 fF/mm)
– 20M logic transistors
• Average width: 12 λ
– 180M memory transistors
• Average width: 4 λ
• Static CMOS logic gates: activity factor = 0.1
• Memory arrays: activity factor = 0.05 (many banks!)
• Estimate dynamic power consumption per MHz.
Clogic   20  106  12  0.05m /   2 fF / m   24nF
Cmem  180  106   4  0.05 m /   2 fF /  m   72nF
Pdynamic  0.1Clogic  0.05Cmem  1.2  f  8.6 mW/MHz
2
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Static (leakage) power
• Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
Vgs Vt
I ds  I ds 0e
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nvT
Vds


vT
1  e 


Leakage example
• The process has two threshold voltages and two oxide
thicknesses.
• Subthreshold leakage:
– 20 nA/m for low Vt
– 0.02 nA/m for high Vt
• Gate leakage:
– 3 nA/m for thin oxide
– 0.002 nA/m for thick oxide
• Memories use low-leakage transistors everywhere
• Gates use low-leakage transistors on 80% of logic
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Leakage power (continued)
• Estimate static power:
– High leakage:
– Low leakage:
 20  10   0.2 12  0.05m /    2.4  10 m
 20  10   0.812  0.05m /   
180  10   4  0.05m /    45.6  10 m
6
6
6
6
I static   2.4  106  m   20nA /  m  / 2   3nA /  m   
 45.6  10 m   0.02nA / m  / 2   0.002nA / m 
6
 32mA
Pstatic  I staticVDD  38mW
 If no low leakage devices, Pstatic = 749 mW (!)
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6
Techniques for low-power design
• Reduce dynamic power
–
–
–
–
Pdynamic  CVDD 2 f
: clock gating, sleep mode
C: small transistors (esp. on clock), short wires
VDD: lowest suitable voltage
f: lowest suitable frequency
I1
I2
Clock
O1
I3
I4
Enable
I5
I
6
Clock Gating
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O2
critical
path
only reduce supply voltage of
non critical gates
Dynamic power reduction via dynamic VDD scaling
• Scaling down supply voltage Pdynamic  CVDD f
2
– reduces dynamic power
– reduces saturation current
 increases delay  reduce the frequency
Dynamic voltage scaling (DVS): Supply and voltage of
the circuit should dynamic adjust according to the
workload of our circuits and criticality of the tasks
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Reducing static power
• Reduce static power
– Selectively use low Vt devices
– Leakage reduction:
- stacked devices, body bias, low temperature
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Leakage reduction via adjusting of Vth
• Leakage depends exponentially on Vth. How to control Vth?
– Remember: Vth also controls your saturation current  delay
1. Body Bias
2. Oxide thickness
Sol1: statically choose high
Vt cells for non critical gates
I1
I2
O1
I3
I4
I5
I
6
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O2
critical
path
Sol2: dynamically adjust the bias of
the body
• idle: increase Vt (e.g. by applying
–ve body bias on NMOS)
• Active: reduce Vt (e.g.: by
applying +ve body bias on NMOS)
Leakage reduction via Cooling
 Impact of temperature on leakage current
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Summary
We are still in chapter 4:
• We covered delay and power estimation
• Next time, we going to move into
integrating the impact of wires into
delay/power calculations
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