Transcript lecture18 - Brown University

Design and Implementation of VLSI Systems
(EN1600)
Lecture 18: Scaling Theory
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2008
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’08
Moore’s Law
Moore’s Law. The number of transistors in an integrated circuit
doubles every 2 years.
IBM Cell
234M transistors in
die size of 221 mm2
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Scaling of MOS transistors
1.2nm
minimum feature size
(gate length)
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Current oxide thickness ~
1.0 – 2.0nm thickness 
3 – 4 atomic layers of
oxide
Power supply
voltage
scaling
Scaling
Scaling of lithographic wavelength
Fewer and fewer companies can
afford to have their own foundries
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Avg transistor price is 0.1 μcent!
Number of transistors shipped
Device scaling
(very idealistic NMOS transistor)
(scaled down by L)
scale
doping increased by
a factor of S
Increasing the channel doping density decreases the depletion width
 improves isolation between source and drain during OFF status
 permits distance between the source and drain regions to be scaled
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Implications of ideal device scaling
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Historically frequency scaled by more than S
Intel VP Patrick Gelsinger (ISSCC 2001)
“If scaling continues at present pace, by 2005, high speed
processors would have power density of nuclear reactor, by
2010, a rocket nozzle, and by 2015, surface of sun.”
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Scaling of standby (leakage) power
Standby power
qV
Poff
1 (  mkTt )

e
tox
bottleneck
 Even if Vt is kept constant after scaling, Poff scales up by S if tox is
scaled down by S
 Vt must be scaled down if VDD is scaled down (otherwise ISAT is
weaker and transistor is slow)
 Standby power would further increase by 10 for every 0.1V
reduction of Vt
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Power supply voltage (Vdd)
Power/performance tradeoffs
higher
active power
higher
leakage
increasing
performance
Threshold voltage (Vt)
[Taur, 01]
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Interconnect scaling
w
t
s
h
l
w: width of interconnect (layer dependant)
s: spacing between interconnects with same layer
h: dielectric thickness (spacing between interconnects in two
vertically adjacent layers)
l: length of interconnect
t: thickness of interconnect
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Constant thickness scaling versus reduced
thickness scaling
reduced thickness scaling
l
w
constant thickness scaling
l
w
t
t
w
S
t
S
l
S
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w
S
t
l
S
Implications of ideal interconnect scaling
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Interconnect delay is dominating gate delay
bottleneck
Repeaters can help but…
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With scaling the reachable radius of a buffer
decreases  we need more and more buffers
bottleneck
repeaters required to
buffer Itanium global
interconnects
 A corner-to-corner (BL-UR) wire in Itanium (180nm) requires 6
repeaters to span die
 Repeaters consume chip area; consume power; add vias
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Summary
Done with chapter 4:
 Delay estimation
 Power estimation
 Interconnects and wire engineering
 Design Margins
 Scaling theory
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