Transcript lecture34 - Brown University

Design and Implementation of VLSI Systems
(EN0160)
Lecture 34: Design Methods (beyond Tanner Tools)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Maxfield/Newnes]
S. Reda EN160 SP’07
Stage I. IC Design, Verification, and Test
Ideas
Specification
simulation/
verification
Design
schematics
C-based design
(SystemC)
HDL (Verilog/VHDL)
Test-structure
Insertion
Synthesis
gate-level
design
S. Reda EN160 SP’07
library
Stage II. IC Physical Implementation Flow
Custom/Application Specific IC (ASIC)
FPGAs
gate-level circuit
Floorplanning/placement
Floorplanning/placement
repeater insertion
clock tree
synthesis
P/G network /
routing
metal fill
insertion
Timing analysis
download
Parasitic
extraction
Power
analysis
Signal Integrity
DRC/LVS
mask generation
/ OPC
reticles/masks
S. Reda EN160 SP’07
routing
Stage III. Fabrication and Packaging
reticles
fabricate wafer
Test dies
dice and package the
good ones
chips
S. Reda EN160 SP’07
Stage I. IC Design, Verification, and Test
Ideas
Specification
verification
Design
schematics
C-based design
(SystemC)
HDL (Verilog/VHDL)
Test-structure
Insertion
Synthesis
gate-level
design
S. Reda EN160 SP’07
Library
Design Entry
System
VHDL
Behavioral
(Algorithmic)
Verilog
Functional
(RTL,
Boolean)
Textual HDL
Graphical State Diagram
When clock rises
If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Structural
(Gate, Switch)
VITAL
- Relatively easy to learn
- Fixed data types
- Interpreted constructs
- Good gate-level timing
- Limited design reusability
- Limited design management
- No structure replication
Top-level
block-level
schematic
- Relatively difficult to learn
- Abstract data types
- Compiled constructs
- Less good gate-level timing
- Good design reusability
- Good design management
- Supports structure replication
System
Untimed
Graphical Flowchart
Block-level schematic
SystemC 2.0
Algorithmic
Behavioral/
Transactionlevel
RTL
S. Reda EN160 SP’07
SystemC
1.0
Timed
Functional Simulation
Make sure your design is logically correct.
S. Reda EN160 SP’07
Synthesis
Synthesis transforms HDL to gates
if
SEL == “00“ then Y
elseif SEL == “01“ then Y
elseif SEL == “10“ then Y
else
Y
end if;
=
=
=
=
A;
B;
C;
D;
if (B > C)
then Y = A + B;
else Y = A + C;
end if;
Resource
Sharing = ON
Resource
Sharing = OFF
A
2:1 MUX
2:1 MUX
D
+
A
2:1 MUX
+
B
C
B
Y
C
Y
A
>
SEL == 10
SEL == 01
SEL == 00
B
Total LUTs = 32
Clock frequency = 87.7 MHz
Y
+
C
>
Total LUTs = 64
Clock frequency = 133.3 MHz (+52% !)
Synthesis has to be “smart”
S. Reda EN160 SP’07
Verification
• We cannot try all possible input combinations to check
our design
• How can we verify that our synthesizer is correct?
• Imagine you are designing a traffic light controller, how
can you guarantee that the light will not be
simultaneously green for both directions?
• Formal verification uses mathematical techniques to
verify certain properties of your design.
S. Reda EN160 SP’07
Stage II. IC Physical Implementation Flow
Custom/Application Specific IC (ASIC)
FPGAs
gate-level circuit
Floorplanning/placement
Floorplanning/placement
repeater insertion
clock tree
synthesis
P/G network /
routing
metal fill
insertion
Timing analysis
download
Parasitic
extraction
Power
analysis
Signal Integrity
DRC/LVS
mask generation
/ OPC
reticles/masks
S. Reda EN160 SP’07
routing
Fast timing analysis using static timing
analysis (STA)
C17 from ISCAS’85 benchmarks
I1
I2
O1
I3
I4
I5
I6
O2
• What is the worst delay of this circuit without regard to the dynamic
input patterns?
• What are the critical path(s) that lead to this delay?  perhaps timing
can be improved if we adjust them
S. Reda EN160 SP’07
Floorplanning and placement
rows
I/O pads
Floorplanning (chip outlining) is a small scale 2-D assignment problem
 determines positions for large blocks of logic/memory
[legal placement]
[illegal placement]
Placement of standard cells is a large-scale 2-D assignment problem
 determines positions for thousands/millions of standard cells
S. Reda EN160 SP’07
Clock tree synthesis
• Clock net(s)  delivers the periodic generated clock signal to FFs
• Design objectives:
Zero-or prescribed skew
minimum wirelength
minimize buffers for signal integrity
data
Minimum wirelength
zero-skew tree for 64 FFs
FF
FF
minimize demand on
metal resources and
reduces power
extra delay
clock
[Kahng et al., TCAS’92]
S. Reda EN160 SP’07
minimize #buffers
and maintain SI
skew can lead to
setup/hold times
violations
Buffering (repeater insertion) for timing and signal
integrity
The situation is complicated in case of multi-pin nets:
sink
What is the minimum
number of repeaters to
meet timing on this net?
source
S. Reda EN160 SP’07
Repeater estimation
for Itanium
sink
Repeater Stations
Design and analysis of power supply networks
• Power supply network delivers
Vdd/Gnd signals to all components.
[Blaauw et al., DAC98]
Main challenges:
1. IR drop: voltage at delivery point is
degraded than the ideal voltage
• performance drop
• signal integrity problems
PowerPC 750 power grid
2. electromigration
PowerPC 750 IR-drop map
S. Reda EN160 SP’07
Routing
Objective: determine routes (tracks, layers, and vias) for each net
such that the total wirelength is minimized.
 Be careful with routing critical nets and clock nets
pin p1
cell
congestion
pin p2
Do you want this to happen
to a net that belongs to the
critical path?!
S. Reda EN160 SP’07
Routing and parasitic extraction
 Multi-pin nets add more complexity in routing
create vias
sink
map to layers
source
sink
 After all routes are determined, you can calculate the
parasitic capacitance between each wire and its neighbors
S. Reda EN160 SP’07
Fill insertion
• CMP (chemical mechanical
polishing) is executed for
each layer before buildup of
other layers
Downforce
Wafer carrier
Polishing pad
Slurry dispenser
Wafer
Polishing
slurry
Rotating
platen
• Remember the DRC
violations from L-Edit! How
can metal fill insertion helps
in smoothing surfaces?
Features
Area fill
features
[(animation is not technically correct!]
[Photos are form Quirk/Serda]
Post-CMP ILD thickness
S. Reda EN160 SP’07
Mask preparation and resolution
enhancement techniques (RET)
MEBES
original layout
GDSII
fractured layout
fractured layout into polygons
(rectangles and trapezoids)
S. Reda EN160 SP’07
[mask writer uses electron
beam for printing patterns]
Mask preparation and resolution
enhancement techniques (RET)
Light source
193nm
130nm feature
[Schellenberg, IEEE Spectrum’03]
S. Reda EN160 SP’07
Stage III. Fabrication and Packaging
reticles
fabricate wafer
Test dies
dice and package the
good ones
chips
S. Reda EN160 SP’07
Fabrication and Test
• Testing
– Functional (yield)
3.0Ghz
• How many circuits work (have no defects)?
3.2Ghz
3.1Ghz
3.1Ghz
3.1Ghz
3.1Ghz
2.9Ghz
F
3.1Ghz
2.9Ghz
F
– Delay/Power (parametric yield)
percentage of chips
• What is the speed and power of the ones that work?
S. Reda EN160 SP’07
Manufacturers speed bin their chips
and sell them according to their
performance
Dicing and packaging
reticles
dice
wafer
S. Reda EN160 SP’07
Packaging choices
S. Reda EN160 SP’07
Summary
• Overview of IC design flow
• We are done with main lectures
• We meet in exactly one week on May 4th to give
your project presentations
S. Reda EN160 SP’07