Transcript Slide 1

Abstract
A comparison between conventional static
CMOS and pseudo-NMOS is presented
for supply voltages from 100 mV to 500
mV and frequencies from 1 kHz to 100
MHz. Standard, forward, and dynamic
body-biased inverters are compared with
respect to speed, power, and energy
performance.
Test Environment
Energy Comparison of Conventional CMOS
and Pseudo-NMOS at Ultra-Low Voltages
David Wolpert and Paul Ampadu
Electrical and Computer Engineering Dept.
University of Rochester
<wolpert, ampadu>@ece.rochester.edu
Results: Delay, Power
• Delay
– For the examined region, forward body-biased
pseudo-NMOS exhibits superior speed performance
• Power
– Standard body-biased CMOS inverters exhibit
superior power performance for the majority of the
region examined
– Near fop,max, pseudo-NMOS inverters dissipate less
power than CMOS inverters
– CMOS inverters are shown to vary significantly with
clock frequency while the pseudo-NMOS inverters
change very little with clock frequency
PDP vs. VDD vs. Frequency
• TSMC 0.18 µm with Cadence Spectre
• Input buffer and output inverters match the
logic style and body-bias of the UUT
• UUTs are resized at each voltage for
symmetric delay
Results: PDP
• PDP plot is divided into four regions of
superiority
– High voltage/low frequency regions favor:
standard body-biased CMOS
– Low voltage and mid-range frequency regions favor:
forward body-biased CMOS
– High frequency regions favor:
forward body-biased pseudo-NMOS
– Low voltage/low frequency regions favor:
standard body-biased pseudo-NMOS
Body Biasing Methods
Standard, dynamic [1], and forward body
biases are used to vary the threshold
voltage of the transistor [2]:
VT  VT 0  

 2 F  VSB  2 F

Power vs. VDD vs. Frequency
Conclusions
Delay vs. VDD vs. Frequency
• When designing for speed
– Forward body-biased pseudo-NMOS
• When designing for power
Units Under Test
CMOS and pseudo-NMOS (pNMOS)
inverters using each body biasing method:
– Fclk << fop,max: Standard body-biased CMOS
– Fclk ≈ fop,max: Forward body-biased pseudo-NMOS
– In between: Forward body-biased CMOS
• When designing for PDP
–
–
–
–
Fclk > 0.1fop,max: Forward body-biased pseudo-NMOS
Fclk < 0.001fop,max: Standard body-biased CMOS
In between: Forward body-biased CMOS
At extremely low voltages (<120 mV): Standard bodybiased pseudo-NMOS
Acknowledgement
Power Behavior Comparison
• Pseudo-NMOS is limited by static power
dissipation
• CMOS is limited by dynamic power
dissipation
CMOS Power Dissipation
Thanks to the EdISon Lab: Dr. Amos Kuditcher,
Bo Fu, and Qiaoyan Yu for their inspiration,
guidance, and support.
References
1.
Pseudo-NMOS Power Dissipation
2.
F. Assaderaghi, et al., “A dynamic threshold voltage
MOSFET(DTMOS) for ultra-low voltage operation”,
IEEE International Electron Devices Meeting, pp. 809812, 1994.
J. Kao, M. Miyazaki, A. Chandrakasan, “A 175-mV
multiply-accumulate unit using an adaptive supply
voltage and body bias architecture”, IEEE J. SolidState Circuits, vol. 37, no. 11, November 2002, pp.
1545-1554.
© 2005 Edison Lab