Transcript lecture17 - Brown University

Design and Implementation of VLSI Systems
(EN0160)
Lecture 17: Static Combinational Circuit Design (1/2)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
How to convert an AND/OR to a NAND/NOR
network?
Sketch a 2 by 1 multiplexer design using AND, OR, and
NOT gates.
D0
S
Y
D1
S
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Converting AND/OR networks to
NAND/NOR networks
• Start with network of AND / OR gates
• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
D
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Y
(d)
Compound gates
• Logical Effort of compound gates
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Delay calculation example
• The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
D0
S
Y
D1
S
H = 160 / 16 = 10
B=1
N=2
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D0
S
D1
S
Y
Solution: simple versus compound for the
MUX case
D0
S
Y
D1
S
D0
S
D1
S
Y
P  22 4
G  (4 / 3) (4 / 3)  16 / 9
F  GBH  160 / 9
fˆ  N F  4.2
P  4 1  5
G  (6 / 3) (1)  2
F  GBH  20
fˆ  N F  4.5
D  Nfˆ  P  12.4
D  Nfˆ  P  14
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Annotating design with transistor sizes
• Annotate your designs with transistor sizes
that achieve this delay.
8
8
8
8
25
25
25
8
8
Y
25
10
10
10
10
24
6
6
12
6
6
Y
8
8
16
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160 * (4/3) / 4.2 = 50
16
160 * 1 / 4.5 = 36
Parasitic modeling
• Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33
2
2
A
2
B
2x
Y
6C
2C
If input arrival time is known
–Connect latest input to inner terminal
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Asymmetric gates
• Asymmetric gates favor one input over another
• Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input
– So total resistance is same
•
•
•
•
•
gA = 10/9
gB = 2
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
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Symmetric gates
• Inputs can be made perfectly symmetric
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2
2
A
1
1
B
1
1
Y
Skewed gates
• Skewed gates favor one edge over another
• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
• Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
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Hi- and Lo-Skew
• Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed inverter
delivering the same output current for the same
transition.
• Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction
• But larger for the other direction
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Catalog of skewed gates
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