Transcript Microelectronic System Design

Welcome to CSE 143!
Microelectronic System Design
Spring 2009
Instructor: Rajesh K. Gupta, [email protected]
Welcome!

Course Objective:


Provide an introduction to microelectronic system design
Course Orientation:
a systems view of the design and design process, not
components
 system engineering issues related to performance, quality
 automation-centric design: tools and methodologies.


You will not learn:
microelectronic device design, physics, process technology
 circuit, logic modeling, design, synthesis, simulation
 computer architecture
 CAD algorithms, writing CAD tools.


You should get skills in

HDL-based circuit, system modeling, synthesis,
optimization.
Course Organization

There are three basic parts to the course
Review of microelectronics, circuits, process technology
 Structured VLSI design: design styles and global issues
 HDL-based modeling, synthesis and optimization


Not necessarily covered in that order

Course logistics described on the class web-page:
http://mesl.ucsd.edu/gupta/cse143.html
Section ID: 656577
 Lectures: Tu/Th 5-6:30PM CENTER 217A
 Office Hours:


Wed 2-4, call or drop by (822-4391, CSE 2120)
Lectures
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Welcome, Introduction to Microelectronic Circuits
and Systems (Thursday, March April 2, 2009)
Review of Microelectronic Processing and Devices
Circuit Styles, Structured VLSI Design
Clocking
Microsystem Modeling using HDLs
Simulation versus Synthesis using VHDL
From Modeling to Circuit Synthesis: Global Issues
Design for Low Power
Architectural Designs
Design Verification
Design for Test
Questions?
Three Trends Driving Microelectronic
Systems Design

Trend 1: Relentless Digitization of Signals and Systems
Courtesy: Paul Gray, UC Berkeley (ISSCC97)
1. GaAs, Si Bipolar
2. Si Bipolar, BiCMOS
3. CMOS
Microelectronic System Trends -- 2

Trend 2: increasing use of “embedded intelligence”

variety of (multiple) compute engines available on-chip
Cellphone Baseband
Graphics Controller
Microelectronic System Trends -- 3

Trend 3: Networking of embedded intelligence

multiple comm. front-ends, networking available on-chip
 The consequence:


smart “spaces”, intelligent interfaces, sensor networks
Integrated circuit chips are driving tremendous capability
increases
Pentium 3 & Pentium 4



28.1M transistors
106 mm^2 die size
0.18 micron, 6-layer metal CMOS




Source: Mani Srivastava, UCLA
42M transistors
217 mm^2 die
0.18-micron process
2GHz clock
Microprocessors
Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."
Moore’s Law Defines The Competitive
Necessity
Die
Die size
size grows
grows by
by 14%
14% to
to satisfy
satisfy Moore’s
Moore’s Law
Law
Transistors
Transistors on
on lead
lead microprocessors
microprocessors double
double every
every 22 years
years
1000
100
2X growth in 1.96 years!
10
486
1
Courtesy, Intel
P6
Pentium® proc
Die size (mm)
Transistors (MT)
100
386
286
0.1
8086
8080
8008
4004
8085
0.01
0.001
1970
1980
P6
Pentium
® proc
486
10
386
8080
8008
4004
Courtesy, Intel
8086
8085
286
~7% growth per year
~2X growth in 10 years
1
1990
Year
2000
2010
1970
1980
1990
Year
Lead
Lead microprocessors
microprocessors frequency
frequency doubles
doubles every
every 22 years
years
2010
100
10000
Power (Watts)
2X every 2 years
1000
Frequency (Mhz)
2000
P6
100
Pentium ® proc
486
10
8085
1
0.1
1970
8086 286
386
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
8080
Courtesy, Intel
8008
4004
0.1
1971
1980
1990
2000
2010
1974
1978
1985
Year
1992
2000
The ITRS: Tao of Scaling
http://public.itrs.net
2007
 0.065 micron
 6.7 GHz on chip clock
 9 wiring levels
 600-3000 pins
 Vdd=0.7-1.1V
 3.5W / 104W / 190W
 DRAM:
4.29 Gb/chip, 183 mm^2, 2.35 Gb/cm^2
 MPU
386 Mtrans/chip, 140 mm^2, 276.1 Mtrans/cm^2

Source: Ken Yang, UCLA
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
Vin
Vout
DEVICE
G
S
n+
Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."
D
n+
Design Process

Conceptualization: function & structure


Architecture: structure and organization


logic synthesis, logic verification, static timing analysis
Circuit implementation: transistors


microarchitectural implementation
Logical implementation: gates, modules


HLM, behavioral modeling
circuit simulations
Physical design, verification

floorplanning, placement, routing, dynamic timing analysis
Many Implementation Choices
Microprocessors
 Domain-specific processors

Speed
Power
Cost
DSP
 Network processors
 Microcontrollers

ASIPs
 Reconfigurable SoC
 FPGA
 Gate-array
 ASIC

High
Low
Volume
E.g. Degree of Customization of
Processor Architecture


The architecture of the computation engine used to
implement desired functionality
Processor does not have to be programmable

“Processor” not equal to general-purpose processor
total = 0
for i = 1 to N loop
total += M[i]
end loop
Controller
Datapath
Controller
Datapath
Controller
Datapath
Control
logic and
State register
Control logic
and State
register
Registers
Control
logic
index
Register
file
IR
PC
General
ALU
IR
Custom
ALU
State
register
Data
memory
total = 0
for i =1 to …
General-purpose (“software”)
+
PC
Data
memory
Program
memory
Assembly code
for:
total
Data
memory
Program memory
Assembly code
for:
total = 0
for i =1 to …
Application-specific
Single-purpose (“hardware”)
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
General-purpose Microprocessors

Programmable device used in a variety of
applications


Features



Program memory
General datapath with large register file and
general ALU
User benefits



Also known as “microprocessor”
Low time-to-market and NRE costs
High flexibility
“Pentium” the most well-known, but there
are hundreds of others
Controller
Datapath
Control
logic and
State register
Register
file
IR
PC
Program
memory
General
ALU
Data
memory
Assembly code
for:
total = 0
for i =1 to …
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Application-specific Instruction
Processors, ASIP

Programmable processor optimized for a
particular class of applications having
common characteristics


Features




Compromise between general-purpose and
single-purpose processors
Program memory
Optimized datapath
Special functional units
Benefits

Some flexibility, good performance, size and
power
Controller
Datapath
Control
logic and
State register
Registers
Custom
ALU
IR
PC
Program
memory
Data
memory
Assembly code
for:
total = 0
for i =1 to …
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Single-purpose ‘Processors,’ or ASIC

Digital circuit designed to execute exactly
one program


Features



a.k.a. coprocessor, accelerator or peripheral
Contains only the components needed to
execute a single program
No program memory
Benefits



Fast
Low power
Small size
Controller
Datapath
Control
logic
index
total
State
register
+
Data
memory
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
E.g. ASIC
ASIC Features
Area: 4.6 mm x 5.1 mm
Speed: 20 MHz @ 10 Mcps
Technology: HP 0.5 mm
Power: 16 mW - 120 mW (mode
dependent) @ 20 MHz, 3.3 V
Avg. Acquisition Time: 10 ms to 300 ms

A direct sequence spread spectrum (DSSS) radio
receiver ASIC (UCLA)
The Implementation Choice is Important
The Co-design Ladder

In the past:



Hardware and software
design technologies were
very different
Recent maturation of
synthesis enables a unified
view of hardware and
software
Hardware/software
“codesign”
Sequential program code (e.g., C, VHDL)
Behavioral synthesis
(1990's)
Compilers
(1960's,1970's)
Register transfers
Assembly instructions
RT synthesis
(1980's, 1990's)
Assemblers, linkers
(1950's, 1960's)
Logic equations / FSM's
Machine instructions
Logic synthesis
(1970's, 1980's)
Logic gates
Microprocessor plus
program bits: “software”
Implementation
VLSI, ASIC, or PLD
implementation: “hardware”
The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Core-based Design: System on Chip

SC3001 DIRAC chip (a radio receiver) from Sirius
Communications
Reconfigurable SoC
Other Examples
Atmel’s FPSLIC
(AVR + FPGA)
Altera’s Nios
(configurable
RISC on a PLD)
Triscend’s A7 CSoC
IP-based Design
[Vincentelli]
Map from Behavior to Architecture
[Vincentelli]
Summary: Microsystems in New
“Spaces”

Generational shift in computing devices
lot more of everything: computing, networking, communications
 lot less of power, energy, volume, weight, patience
 Application
Instrumentedis everything, the possibilities are limitless

wide-area spaces

Internet end-points
System architectures are due for an overhaul
the architectures are (radically) changed/challenged
 the programming context is changed
 the system software contract is changed
 new awareness: location, power, timing, reactivity, stability

In-body, in-cell, in-vitro spaces
Personal area spaces
Next Lecture: Overview of Semiconductor Devices/Processes.