Transcript Semiconductor Process Technology

io 1
Lecture
Introduction to IC Fabrication
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HISTORY
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What is Semiconductor Process Technology?
 The technology to produce IC microchips
 IC chips are the backbone of the computer industry and have spurred
related technologies such as software and internet
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 Every product of the information age is an offspring of IC technology
 IC chips increasingly control functions in cars, TVs, VCRs, cameras,
mobile phones, toys, etc.
 The current technology is as a result of years of research and
development, taken many thousands of scientists, engineers and
technicians.
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The Evolution of IC
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First Transistor, Bell Lab 1947
John Bardeen and Walter Brattain, demonstrated
a solid state device made from germanium. They
observed that when electrical signals were applied
to contacts on germanium, the output power was
larger than the input. These results were published
In 1948.
William Shockley, found out how the bipolar transistor
functioned and published the theory in 1949.
Three of them shared the Nobel Prize in physics in
1956,
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First Transistor and Its Inventors
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 Semiconductor industry developed rapidly and germanium based
transistor quickly replaced vacuum tubes in electronics equipment
due to:
 smaller size
 lower power consumption
 lower operating temperature
 quicker response time
 Single crystal silicon and germanium based devices introduced in
1950 and 1952 respectively (better defect control, hence higher yield).
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 Shockley left Bell Labs in 1956, to start his own lab in San Francisco Bay,
California. Nowadays known as Silicon Valley. His lab has attracted
talented scientist such as Robert Noyce and Gordon Moore.
 Gordon Moore and Robert Noyce left Shockley in 1957 to start Fairchild
Semiconductor.
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First IC Device by Jack Kilby, Texas Instruments
1958
1st fabricated by Bell Labs in 1958. Jack Kilby
demonstrated functional IC, fabricated on
germanium strip consists of;
 one transistor
 one capacitor
 3 resistors
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First Silicon IC Chip by Robert Noyce, Fairchild
Camera, 1961
Fairchild Semiconductor produced the 1st commercial
ICs in 1961. This IC consists of only 4 transistors sold
for USD 150 a piece.
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NASA was the main customer.
In 1968, Robert Noyce cofounded Intel Corp. with
Andrew Groove and Gordon Moore.
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Moore’s Law
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Moore’s Law, Intel Product
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IC Integration Scale
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Feature Size and Wafer Size
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Road Map Semiconductor Industry
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Limit of IC Size
Is there a limit for the minimum feature size?
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Limit of IC Device
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IC Product Category
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OVERVIEW ON IC MANUFACTURING
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IC Manufacturing
 A very complicated process, involves;
 Circuit design
 Manufacturing material
 Clean room technology, processing, equipment
 Wafer processing technology
 Die testing
 Chip packaging and final test
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IC Manufacturing Flow
Design
Mask info to MASK-SHOP + GDSII file
Mask making
Generate runcard
Wafer Preparation
Front-end Processes (individual transistor)
Deposition
Oxidation
Diffusion
Photolithography
Etch (wet and dry)
Implantation
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 Backend Process
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Deposition (oxide, nitride etc)
Metalization
Rapid Thermal Process
Lithography & Etch
 Test (Parametric and Functional)
 Packaging
 Final Test
IC Manufacturing Processes
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IC Manufacturing Processes
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IC Design: Idea to Design Synthesis
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IC Design: Architecture to Layout
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 Architectural Design – Defines the application operating system and
devides modules for system.
EEPROM Design Layout
GND
A2
Control Logic (Master)
A1
A0
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Charge Pump
Dec Y
E/W
circuit
Decoder Xe
16K-bits Memory Cell
E/W
circuit
Decoder Xr
SDA
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SCL
Timer
WP
VCC
 Logic Design – Puts logic units such as adders, gates, inverters and
registers into each module and run subroutines in each module .
 Circuit / Transistor Design – Individual transistors are laid out in each
logic unit.
 Layout – To transfer from schematic to layout
VDD
S
pMOS
D
VIN
VOUT
D
nMOS
S
VSS
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IC Design: Design Flow
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Wafer Fabrication: From Design to Wafer
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IC Design: 1st IC
1st IC design by hand (Jack Kilby)
Currently, hundreds of designers work
on single product to design, validate
and lay outed will take several months
to complete with the help of CAD
tools.
Main considerations;
 performance
 die size
 design time and cost
 testability
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IC Design: State of The Art IC
CMOS Inverter - basic building block of digital MOS design
Layout
Cross section
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IC Design: Layout and Mask s of CMOS Inverter
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Mask / Reticle
 After IC design is completed, generated layout image is printed on a
piece of quartz glass coated with a layer of chromium.
 A laser beam projects the layout image onto the photoresist coated
chrome glass surface.
 Photon change the chemistry of the exposed photoresist via a photo
chemical reaction, and later dissolved in a base developer solution.
 A pattern etching removes the chromium at the exposed area.
 Therefore, it transfers the image of the IC layout to the quartz glass.
 This is done at mask shop
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Mask / Reticle
 Mask – Covers the whole wafer, used in projection, proximity and contact
lithography technique.
 Reticle – Covers only part of the wafer, employed in step and repeat
lithography technique.
MASK
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RETICLE
Typical Wafer Fabrication Process Flow
 Around 500 process steps to complete IC fabrication
 Involves 20 masking steps
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OVERVIEW ON WAFER FABRICATION
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Wafer Fabrication
Objectives
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Why Yield Is Important?
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Wafer Yield
 The ratio between number of good wafers after finishing all the process
steps, and total number of starting wafers .
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Die Yield
 The ratio between number of good dies per total of dies on the tested
wafer after functional probe test.
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Packaging Yield
 The ratio between number of good chips after finishing all the packaging
steps, and total of chips packaged.
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Overall Yield
Wafer yield depends mainly on processing and wafer handling.
 Careless handling and robot malfunction could break wafers
 Faulty process such as misaligned during lithography, large amount of
particles, poor process uniformity, etc can also ruin wafers.
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How Does Fab Make Money
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How Does Fab Make (Loss) Money
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Defects and Yield
 Y – overall yield
 D – defect density (minimum level determined by facilities)
 A – chip area (die size)
 n – number of processing steps
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Yield and Die Size
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Yield Curve
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Typical Production Wafer
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Typical Production Wafer
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Why Cleanroom ?
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Cleanroom
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Cleanroom Class
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Cleanroom Class
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Cleanroom Class (Definition of Airborne
Particulate)
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Effect of Particles on Mask
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Effect of Particles on Wafer
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Cleanroom Structure
Main features;
 raised floor
 laminar air flow
 HEPA filters
 higher pressure
 controlled humidity
and temperature
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Gowning Area
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Typical Wafer Process Flow
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Typical Wafer Process Flow
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Typical Process Bay
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Wafer Test
 Parametric Test (Wafer Acceptance Test Data)
 Functional Test (Die Yield)
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Device Specifications (Transistor)
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Device Specifications (Resistance)
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Parametric Test Result (WAT Data)
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Functional Test
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Packaging
4 Main Purposes;
 to provide physical protection for the IC chip
 to provide a barrier layer against chemical impurities and moisture
 to connect the IC chip to the electrical circuit board
 to dissipate heat generated during chip operations
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Main Packaging Steps
 Wafers coated with protective layers on the surface, mechanically
polished on the wafer backside to reduce thickness (600 to 300 um)
 A thin layer of gold is coated at the wafer backside
 Protective layer at the wafer surface is removed, and wafer backside
is taped to on a solid frame. Then wafer sawing process.
 Die sorting (to pick up good dies)
 Die attach (to attach good dies to a packaging socket)
 Wire bonding
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Chip Bond Structure
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Wire Bonding
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Wire Bonding
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IC with Bonding Pads
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IC Chip Packaging
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Chip with Bumps
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Flip Chip Packaging
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Bump Contact
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Heating and Bumps Melt
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Molding Cavity for Plastic Packaging
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Ceramic Seal
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