Transcript CHAPTE R 13 Output Stages and Power Amplifiers Power

C H A P T E R 13
Output Stages and
Power Amplifiers
Power Amplifiers Power ≈ 1W
Small signal model 不適用
A. I IC I > IC , θ=360
B. IC = 0 , θ=180
Figure 13.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d)
class C amplifier stages.
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A B類. θ > 180
C. θ < 180 ,通訊
Figure 13.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d)
class C amplifier stages.
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定電流
(13.5)
I ≥ |-Vcc +VcE2sat| / RL
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V0(max)
V0(min)
Q1 off
Figure 13.3 Transfer characteristic of the emitter follower in Fig. 14.2. This linear characteristic is obtained by neglecting the change in vBE1
with iL. The maximum positive output is determined by the saturation of Q1. In the negative direction, the limit of the linear region is
determined either by Q1 turning off or by Q2 saturating, depending on the values of I and RL.
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(14.7)
η≡ PL / PS
(14.8)
平均 PL = V02 /2RL
PS = 2 * VCC * I
PD = i c1 * VCE1
PD(max) = i c1 =I
ηmax≡ 25%
Figure 13.4 Maximum signal waveforms in the class A output stage of Fig. 14.2 under the condition I = VCC /RL or, equivalently, RL = VCC /I.
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Push - pull
*無bias I
Figure 13.5 A class B output stage.
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QN
Qp
dead band
Figure 13.6 Transfer characteristic for the class B output stage in Fig. 13.5.
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(14.12)
PL = V02 /2RL
average current = V0 /πRL
(14.13) PS+ = PS- = (V0 /πRL) * VCC
ηmax = π/4 = 78.5% (14.16)
Figure 13.7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion.
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PL – PS = PD
(14) - (12) ----> (19)
PD = 2V0VCC/πRL – V02/2RL
әPD/әV0 = 0
V0 | PD max= 2VCC/π
PD max = 2VCC2/π2RL
Figure 13.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid.
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VI > V0 + 0.7/A0
 QN 即 ON
V0
A0(VI-V0)
Figure 13.9 Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion.
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Figure 13.10 Class B output stage operated with a single power supply.
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Static：i N = i P = IQ
VBB ≈ 2VBE(ON)
VBB bias
(14.26) i
N
V0 = VI + VBB /2 –VBEN (14.24)
* i P = IQ 2
VI > 0 , 且很小 i N ↑ , i P ↓
且很大 i N ↑ ↑ , i P = 0
Figure 13.11 Class AB output stage. A bias voltage VBB is applied between the bases of QN and QP, giving rise to a bias current IQ given by Eq.
(14.23). Thus, for small vI, both transistors conduct and crossover distortion is almost completely eliminated.
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Figure 13.12 Transfer characteristic of the class AB stage in Fig. 13.11.
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(14.28) Rout = ren // rep
= (14.31)
= VT / (i P + i N)
Figure 13.13 Determining the small-signal output resistance of the class AB circuit of Fig. 13.11.
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thermal runaway : temp ↑ , i cN ↑ ↑  temp ↑
*temp ↑  ID(ON) 不變  VD(ON) ↓  VBB ↓  ic ↓  temp ↓
Figure 13.14 A class AB output stage utilizing diodes for biasing. If the junction area of the output devices, QN and QP, is n times that of the biasing
devices D1 and D2, and a quiescent current IQ = nIBIAS flows in the output devices.
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VBE1(1 + R2/R1) =
VBE1
Figure 13.15 A class AB output stage utilizing a VBE multiplier for biasing.
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I bN
IR = VBE1 / R1 (14.32)
I C1
IR
VBE1
V0很大 , I bN不小
I C1↓ VBE1小一點點
 VBB幾乎不變
Figure 13.16 A discrete-circuit class AB output stage with a potentiometer used in the VBE multiplier. The potentiometer is adjusted to yield the desired
value of quiescent current in QN and QP.
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Figure 13.18 An alternative CMOS output stage utilizing a pair of complementary MOSFETs connected in the commonsource configuration. The driving circuit is not shown.
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Figure 13.19
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Figure 13.21
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Figure 13.22
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Tj -T A = θ jA * PD (14.36)
(14.38) PD max = (Tj max -T A ) / θ
jA
PD
TA
Figure 13.24 Maximum allowable power dissipation versus ambient temperature for a BJT operated in free air. This is known as a “power-derating”
curve.
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Figure 13.25 The popular TO3 package for power transistors. The case is metal with a diameter of about 2.2 cm; the outside
dimension of the “seating plane” is about 4 cm. The seating plane has two holes for screws to bolt it to a heat sink. The
collector is electrically connected to the case. Therefore an electrically insulating but thermally conducting spacer is used
between the transistor case and the “heat sink.”
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ӨjA=ӨjC+ӨCA
case
sink
Figure 13.26 Electrical analog of the thermal conduction process when a heat sink is utilized.
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PDmax = Tjmax-Tc / Ө jc
j
c (廠商)
Figure 13.27 Maximum allowable power dissipation versus transistor-case temperature.
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Heat 全沒了
Figure 13.28 Thermal equivalent circuit for Example 14.5.
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i0
Melting wire
(P Dmax)
Emitter crowding
(hot spot)
VBE
V0
Figure 13.29 Safe operating area (SOA) of a BJT.
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Bias VBB
負回授 . *Ri
Figure 13.30 A class AB output stage with an input buffer. In addition to providing a high input resistance, the buffer transistors Q1 and Q2 bias the
output transistors Q3 and Q4.
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Figure 13.31 The Darlington configuration.
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Figure 13.32 The compound-pnp configuration.
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Darlington
compound
Figure 13.33 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained using a VBE multiplier.
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ib1
ics
ie1
平時 Q5 off
iL ↑↑(及 ie1很大)
→Vbe5 ↑(Q5ON)
→ib1↓→ie1 ↓
Figure 13.34 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while
vO is positive.
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Vcs
Power
Amp.
導熱
Sink IQ (並聯)
平時 Q2 off
temp↑→VZ1↑→Ie
1↑→Vb2↑
→Q2 ON
Figure 13.35 Thermal-shutdown circuit.
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Q3.Q4:diff. amp.
Q1.Q2:Vi buffer
Q5.Q6:active load
I3
(14.45)
V0=VS/2
I3
負回授
i/P
主
I4為負F.B.
V0↑→i4↑
→ic4↑
→ic12↑(I3固定)
→ib7↓
O/P
→V0↓
Figure 13.36 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.)
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6 + 9 = 10
Vi/R3 +V0/r2 +Vi/R3=0
10
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Av=-50
Figure 13.37 Small-signal analysis of the circuit in Fig. 14.30. The circled numbers indicate the order of the analysis steps.
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Figure 13.38 Power dissipation (PD) versus output power (PL) for the LM380 with RL = 8V. (Courtesy
National Semiconductor Corporation.)
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Booster 增幅
Q3 ON ,
Ic3 ↑,
→VQ5↓
→Q5 ON
IC5↑↑
Figure 13.39 Structure of a power op amp. The circuit consists of an op amp followed by a class AB buffer similar to that discussed in Section 14.7.1.
The output current capability of the buffer, consisting of Q1, Q2, Q3, and Q4, is further boosted by Q5 and Q6.
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A1 A2 為 power OP .amp
V+
V-
Figure 13.40 The bridge amplifier configuration.
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S
*power MOSFET
VG
N+
VD
N+
P
Figure 13.41 Double-diffused vertical MOS transistor (DMOS).
300u↑
S
N+
P+
N-
N+
VD (500V)
壓降
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*V-groove MOS
(14.46)
iD∝C0*u*(W/L)(VGS-Vt)²
(14.47)
iD∝Usat(VGS-Vt)
定
↓
[(VGs-Vt) /L] * u
Figure 14.42 Typical iD–vGS characteristic for a power MOSFET.
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*Power MOS 無 thermal runaway
ic
*Vgs 小時 , temp ↑ →Vt↓ →id↑
*Vgs 大時, temp ↑ → u ↓→ id ↓
VBE
Figure 13.43 The iD–vGS characteristic curve of a power MOS transistor (IRF 630, Siliconix) at case temperatures of –55C, +25C, and +125C.
(Courtesy Siliconix Inc.)
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Power MOS
Switching faster
Figure 13.44 A class AB amplifier with MOS output transistors and BJT drivers. Resistor R3 is adjusted to provide temperature compensation
while R1 is adjusted to yield the desired value of quiescent current in the output transistors. Resistors RG are used to suppress parasitic
oscillations at high frequencies. Typically, RG = 100 W.
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