Transcript Document

TimeLess Design Automation
Delivering break-through performance
and power to ASIC design
Profile

Founded April 2008

Peter A. Beerel, USC

Georgios D. Dimou, USC

Self-funded to date

Offices located in Calabasas, CA, USA

Currently working with a team of 3 engineers
Activities

EDA tools


Software to enable an asynchronous ASIC flow

Complete solution from RTL to GDSII

Targeting high-performance design

Lower total power than synchronous counterparts
Semiconductor IP

ASIC libraries to support our design styles

Specialized macros that benefit from asynchronous design
Status

Strategic partnership with Fulcrum Microsystems

No commercially-available product offering yet


First prototype product is complete and undergoing testing

Test-chip fabricated and tested successfully in 65nm

Targeting high-performance circuits (1.2 GHz)
Other flavors planned

Exploring partnership opportunities to guide development