Transcript GDG_TIPP_2014_fin_-_rx

Trends in Front-End ASICs
for Particle Physics
Gianluigi De Geronimo
Brookhaven National Laboratory
[email protected] , +1(631)344-5336
TIPP - Amsterdam - June 2014
Outline
• CMOS Technologies
• ASICs for Particle Physics
• Challenges and Paradigm
Microelectronics
Art of combining micrometer-scale components into
a single monolithic device: Integrated Circuit (IC)
~ 20,000 µm
The most widely adopted IC
technologies use the MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
~ 20 µm
D
G
L
S
The Rapid Evolution of Microelectronics
L
Transistor channel length L
10µ
10
µm
100G
V
12
m
3µ
5V
m
2µ
.
1
1µ
100n
> 3GHz
Xbox One 28nm
10-core XEON 32nm
6-core I7 45nm
5V
5V .3V V
m
3 .5
0n nm 2
0
8 00 nm
8V
1. .5V
5 250
m 1 .2V V
n
7V
m 1 .2
.
0
n
0
18 30 nm 1 .1V V
ET
1 0 nm 1 .1 V
F
9 5 m 1 .0 V in
6 5n m 1 0.9 F
4 2n nm
Intel 80486
3 28 nm 4nm
20 6-1
1
10n
10G
1G
100M
10M
1M
100k
Intel 80286
10k
1n
first IC
1960
Intel 4004
1MHz
1970
1980
1k
1990
2000
Year
2010
2020
2030
100
2040
Number of transistors / die
first MOSFET
From Planar FET to FinFET (3D FET)
Planar FET
FinFET (3D FET)
Conducting channels on three sides of a vertical "fin" structure,
providing "fully depleted" operation - introduced in late '90s
• Combine 20nm-Planar FETs and
sub-20nm FinFETs
• 55% drop in power dissipation or
35% boost in speed compared to
28nm-Planar
The Rapid Evolution of Microelectronics
L
Transistor channel length L
10µ
10
µm
100G
V
12
m
3µ
5V
m
2µ
.
1
1µ
100n
> 3GHz
Xbox One 28nm
10-core XEON 32nm
6-core I7 45nm
5V
5V .3V V
m
3 .5
0n nm 2
0
8 00 nm
8V
1. .5V
5 250
1 V
nm m 1.2 2V
7V
.
0
n
0
.
18 30 nm 1 .1V V
ET
1 0 nm 1 .1 V
F
9 5 m 1 .0 V in
6 5n m 1 0.9 F
4 2n nm
Intel 80486
3 28 nm 4nm
20 6-1
1
10n
10G
Exotic Transistors
•1G
single-electron
• carbon-nanotube
•100M
...
10M
1M
100k
Intel 80286
10k
1n
first IC
1960
Si lattice spacing 0.54nm
Intel 4004
1MHz
1970
1980
1990
2000
2010
2020
2030
Number of transistors / die
first MOSFET
1k
100
2040
Year
Introduced in the ’90s, exotic transistors made considerable progress, but are still
far from achieving reproducibility and reliability required by microelectronics
High-Density Interconnects - 2.5D and 3D
· Through-Silicon Via (TSV)
vertical interconnects through active or
passive die - µm diameter
· Micro-Bump / Metal-Metal Bonds
2D interconnects - µm size
2.5D TSV
active dies
micro-bumps
passive Si interposer with planar
and vertical (TSV) interconnects
3D TSV
active die
micro-bumps
active dies with TSVs
flip-chip bumps
stack many dies with different functionalities
The Rapid Evolution of Microelectronics
first MOSFET
L
Transistor channel length L
10µ
10
µm
V
12
m
3µ
TSV
m
2µ
.
1
100n
100G
3D
(TSV)
5V
1µ
3D (FF) + 3D
> 3GHz
2.5D
Xbox One 28nm
10-core XEON 32nm
6-core I7 45nm
5V
5V .3V V
m
3 .5
0n nm 2
0
8 00 nm
8V
1. .5V
5 250
1 V
V
nm m 1.2 2V
.7
0
n
0
.
8
V
1 30 nm 1 .1 V
ET
1 0 nm 1 .1 V
F
9 5 m 1 .0 V in
6 5n m 1 0.9 F
4 2n nm
Intel 80486
3 28 nm 4nm
20 6-1
1
10n
10G
Exotic Transistors
•1G
single-electron
• carbon-nanotube
•100M
...
10M
1M
100k
Intel 80286
10k
1n
first IC
1960
Si lattice spacing 0.54nm
Intel 4004
1MHz
1970
1980
1990
2000
2010
2020
2030
Number of transistors / die
Through-Si Vias
1k
100
2040
Year
Progress heavily driven by consumer electronics
Semiconductor Market
communications
toys
computing
entertainment
Billion Dollars
storage
medical
industrial
control
Year
PP
50M?
PP has little chance to make an impact on evolution
Microelectronics and Particle Physics
data processing
and computing,
communication,
...
Radiation Detectors ?
Require custom-designed front-end electronics frequently
in the form of Application-Specific Integrated Circuits
Front-end ASIC
• optimized front-end circuit
• small physical size
• low power dissipation
• radiation tolerance
• cost (in context of whole detector)
• ...
AMPLEX (1988) - First Large Scale
16 channels, ~800 MOSFETs (~50/ch)
3µm CMOS, 5V, 1.1 mW/ch, 16 mm²
amplifier/filter/track & hold/mux
for Silicon micro-strips at UA2
FE-I5 (2016-17?)
260k pixels, 1G MOSFETs (~4,000/px)
65nm, 1.2V, 0.5-1 W/cm², >400mm²
high complexity/functionality, DSP
for ATLAS vertex hybrid pixels
Institute
WG1
Radiation
WG4
I/O
WG5
Analog
Bari
C
Bergamo-Pavia
A
C
A
Bonn
C
A
B
A
B
B
CERN
B(*)
A
(*)
A
C(*)
A
CPPM
B(*)
A
B
C
C
B
A
Fermilab
A
B
LBNL
B
A
B
LPNHE Paris
A
B
A
A
A
A
A
NIKHEF
A
Padova
A
Perugia
B
Pisa
A
B
WG6
IPs
A
A
B
A
A
B
RAL
ARCHITECTURE
WG3
Sim./Ver
19 institutions
specialized working groups
100 collaborators
(~50 ASIC designers)
New Mexico
PSI
WG2
Top level
A
A
A
C
B
B
Torino
C
B
C
UCSC
C
B
C
B
A
A
B
A
A
A
A
C
A
A
A
2X2 pixel unit
Compare to Evolution of Microelectronics
L
Transistor channel length L
10µ
10
µm
100G
V
12
m
3µ
m
2µ
.
1
1µ
10G
Xbox One
5V
5V
6-core I7
m
0n
0
8
nm
0
25
100n
1G
100M
FE-I4
nm
0
13
nm
65 5nmm
4 2n nm
3 28
10n
FE-I5
10M
VMM
1M
100k
10k
1n
1k
AMPLEX
first IC
1960
1970
Number of transistors / die
first MOSFET
FILAS
1980
1990
2000
2010
2020
2030
100
2040
Year
Delay from characterization, prototyping prices, resources
VMM (2015-16?)
64 channels, >6M MOSFETs (>80k/ch)
130nm, 1.2V, 0.4 W/cm², >110mm²
high complexity/functionality w/DSP
for ATLAS muon spectrometer/tracker
V. Polychronakos
New Small Wheels
sTGC , MicroMegas, 2.3M channels
neighbor
or
64 channels
TGC out (ToT, TtP, PtT, PtP, 6bADC)
logic
data/TGC clock
6-b ADC
CA
peak
shaper
time
test
bias
pulser
tp clock
10-b ADC
8-b ADC
4X
FIFO
DSP
mux
12-b BC
trim
DAC
addr.
temp
ART clock
ART (flag + serial address)
Gray count registers logic
BC clock prompt
analog1
analog2
analog mon.
tk clock
reset
data1
data2
Impact on ATLAS New Small Wheels
2005 - ASM
2015 - VMM
• 60x sensing elements (32k→2M), 10x element density (5→0.5 mm)
• 3x power dissipation (300→15 mW/element)
• comparable data-transfer bandwidth, fully data-driven, discrimination
• trigger primitives, timing measurements, programmable polarity
(1) FE ASICs will become very-high-complexity systems-onchip (SOC) and will require high-density interconnects
Front-end ASICs vs Year
80
Number of designs
60
Number of front-end ASICs for PP
running and in design
2013
~ 60 FE (out of ~140)
~ 35 FE in design
40
20
0
1980
1990
2000
Year
2010
2020
sources: HEPIC 2014 White Paper et al.
(2) The demand for FE ASICs is increasing
Front-End ASICs vs Technology
Number of ASIC Designs in PP
50
40
complexity
availability
prices
resources
Estimate 2013
30
running
in design
all
front-end
20
10
90
nm
65
nm
45
nm
28
nm
80
0n
m
50
0n
m
35
0n
m
25
0n
m
18
0n
m
13
0n
m
0
Technology
(3) PP ASICs are keeping pace with technology
The PP-ASIC Paradigm
Complexity
PP ?
ASIC ?
Demand
Technology
Advances in Particle Physics detectors
are tightly coupled to advances in
ASICs and associated interconnects
Design Groups – Current Status
design groups ≈ 30-40
...
...
...
...
active designs ≈ 30-40
...
... NOvA APV25
MAPS POM
3D FSSR2 ASDQ
PACIFIC ICECAL
FE-I5 CBC LBNE VMM
MAROC3
CLARO
KPIX nEXO
LAPAS ASDCDC SAMPA
BEAN QIE
VELOPIX
ABC ... SAO3
...
CLIC
SALT
TARGET ISR3B
Average one design per group
• institutions leading collaborative efforts
• institutions performing R&D on technologies
One FE-ASIC design currently requires
2-4 full-time designers and 2-4 years
average, from concept to ready-for-production
Design Groups – Current Status
In order to be efficient and maintain state-of-the-art
ASIC groups must:
• develop 1-2 new designs and 2-4 revisions per year
• work with 2 technologies (re-usage & next)
• perform R&D on circuits and technologies
The critical minimum is currently 5-6 designers
Need to diversify while contributing to PP
with an average of 25-30 % of resources
PP currently supports/uses up to 25-30 %
The PP-ASIC Paradigm
Complexity
PP ?
ASIC ?
Demand
Technology
Collaborations ?
• only part of the solution
• communication
• overhead
• lead of large group
The number of ASIC designers has to increase !
involve
non-PP ASIC groups
increase size
of PP ASIC groups
Evolution of Front-End ASIC Design Groups
In order to contribute to future PP detectors
FE ASIC groups need to:
• grow (30-40%)
• increase collaborations (know-how exchange)
• develop/acquire "system-level FE ASIC designer"
• develop/acquire "high-density interconnects“
• align technologies
• evolve and coordinate R&D
PP community needs to contribute with 25-30%
Alternative? Pay companies (hundreds M$)
Aligning Technologies
Collaborations
Long-lasting choice
(re-usage)
(know-how)
90
nm
65
nm
45
nm
28
nm
13
0n
m
18
0n
m
25
0n
m
35
0n
m
50
0n
m
80
0n
m
skip technologies ... ~ jointly
• Specialized groups must perform characterization
• Initial phase of pioneering projects (large groups)
• Some exceptions for specialized technologies
keep < 1W/cm²
Coordinating R&D
R&D on enabling circuits/technologies
• low-power ADCs
• low-power DSP (auto-calib., data red., program., ...)
• low-power high-speed communication (standards)
• low-power low-voltage analogs
• high dynamic range, waveform sampling
• high-density interconnects (2.5D, 3D - incl. sensors)
• cryogenic
• MAPS
• ...
When to exit/enter a technology ?
• exit too late may result in limited collaborations
• enter too early may result in waste of resources
Conclusions
Advances in PP detectors are tightly coupled to advances
in front-end ASICs and associated interconnects
Front-end ASICs:
• dramatic increase in complexity/functionality (SOC)
• increase in demand
• need to keep pace with the technologies
ASIC groups:
• increase size and collaborations (know-how)
• perform R&D towards SOC and interconnects
• align technologies and coordinate R&D
Acknowledgment
G. C. Smith, V. Radeka, BNL Microelectronics, CERN, PP FE ASIC Community
IC Designer in a “Collaboration”
Prototyping Prices
250k
2014 average MPW price
for a 16mm² prototype
Average MPW Price
200k
2014
prices 1/2 every ~5 years
150k
100k
50k
2004
2024?
2019?
28
nm
45
nm
65
nm
90
nm
13
0n
m
18
0n
m
25
0n
m
0
Technology
Prototyping costs are increasing (price, size)