Transcript Application Specific Integrated Circuit Design

ASIC Design
The history of Integrated Circuit (IC)
• The base for such a significant progress
– Well understanding of semiconductor physics
– Capability of purifying the material
– Fine control of IC manufacture process
• One of the most important inventions in our modern
life
– IC has changed our life
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Introduction - 1
Personal computer
Cellular phone
Internet
Wireless communication
Automobile electronics
Medical applications
ASIC Design
In 1947, John Bardeen, Walter Brattain, and William Shockley
invented the first transistor.
Introduction - 2
ASIC Design
In 1958, Jack Kilby and Robert Noyce invented the first
integrated circuit.
Introduction - 3
ASIC Design
Introduction - 4
ASIC Design
Moore’s law
• The performance and density are doubled every 18
months.
• Moore’s law has held for the past 40 year. Let’s look
at
– Moore’s law in microprocessors
– Moore’s law in chip capacity
– Die size growth
– Wafer size (12 inch)
Introduction - 5
ASIC Design
Moore’s Law in Microprocessors
1000
2X growth in 1.96 years!
Transistors (MT)
100
10
486
1
386
286
0.1
0.01
8086
8080
8008
4004
8085
0.001
1970
Introduction - 6
P6
Pentium® proc
1980
1990
Year
Courtesy, Intel
2000
2010
ASIC Design
Evolution in DRAM
Chip Capacity
human memory
human DNA
100000000
10000000
64,000,000
4X growth every 3 years!
16,000,000
Kbit capacity/chip
4,000,000
1000000
1,000,000
book
100000
64,000
16,000
10000
4,000
1000
1,000
256
100
64
10
1980
Introduction - 7
256,000
0.07 m
0.1 m
0.13 m
0.18-0.25 m
0.35-0.4 m
0.5-0.6 m
0.7-0.8 m
1.0-1.2 m
encyclopedia
2 hrs CD audio
30 sec HDTV
1.6-2.4 m
page
1983
1986
1989
1992
1995
Year
1998
2001
2004
2007
2010
ASIC Design
Die Size Growth
Die size (mm)
100
P6
Pentium
® proc
486
10
386
8080
8008
4004
8086
8085
286
~7% growth per year
~2X growth in 10 years
1
1970
Introduction - 8
1980
1990
Year
Courtesy, Intel
2000
2010
ASIC Design
International Technology Roadmap for
Semiconductors (ITRS)
Production year
2002 2003
2004 2005 2006 2007
MPU Gate length (nm) 75
65
53
45
40
35
Clock (GHz)
2.3
3.1
4.0
5.2
5.6
6.7
Metal layers
8
8
8
9
9
9
Supply voltage (V)
1.0
1.0
1.0
0.9
0.9
0.7
Introduction - 9
ASIC Design
Technology has moved into the deep submicron
(DSM) feature size
– The state of the art technology is 22nm feature
size
– Face many new IC design issues due to the increasing
performance requirement and DSM feature size
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Introduction - 10
Design for manufacture (DFM)
New device model
Performance driven design
Distributed circuit parameters
Power dissipation
More powerful CAD tools
ASIC Design
Exploding Mask Costs
Year
1999
2002
2004
2007
Node
.18µm
.13µm
.9µm
.065µm
Cost
$200-400K
$500K-1M
$800K-1.2M
$1-2M
Data
16GB
64GB
256GB
1024GB
• Raster scan patterning exposure time for a 110mm x
110 mm mask is 6.5 hrs and 20 hrs with fine
granularities (60nm vs. 120nm pixel size)
• Largest cost contribution to mask making is mask
exposure time (capital cost ~$20M)
• RET is being absorbed by CAD vendors into layout
verification / tape-out suites.
• RET may move up into routing, placement
Source: Thomas Weisel Partners
Introduction - 11
ASIC Design
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Power delivery and dissipation will be prohibitive
Introduction - 12
Courtesy, Intel
ASIC Design
Power Density (W/cm2)
10000
Power Density
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
Hot Plate
10 4004
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
Year
2000
2010
Power density too high to keep junctions at low temp
Introduction - 13
Courtesy, Intel
ASIC Design
Custom and semi-custom ICs
– Custom designed microprocessors, such as Intel
Pentium
– Semi-custom designed ICs, such as gate array and
FPGA
• Specific circuit structures are introduced to shorten
design cycle
• Tread-off between the design quality and design time
• ASIC chip usually uses custom design to increase the
performance and to reduce the chip cost
• Prototype development usually use the semi-custom
design to reduce the design cycle
Introduction - 14
ASIC Design
Intel Pentium (IV) Microprocessor (custom design)
Introduction - 15
ASIC Design
Design flow
– Traditional design flow
• The design tasks usually can be divided into separated
stages
• Single direction, usually a top-down strategy
– The interplay between different design tasks
becomes important
• Physical phenomena and circuit facts should be
considered at high design levels
– Floorplanning is a challenge
Introduction - 16
This chart only
presents the
basic tasks in
the design
process.
However, the
flow of design
tasks is not a
single direction.
The influence
of the late
design stage
can affect the
early ones.
Design
perspectives
ASIC Design
CAD tools
– Most of today’s IC design are done by using CAD tools.
The major CAD tools are:
• Cadence
– good physical design
– synthesis
• Synopsis
– good high level synthesis
– physical layout
• Mentor Graphics
– analog IC
– verification
• Magma
– physical design, good in time closure
Introduction - 19