Transcript Xilinx XC4000 FPGA devices - Mahanakorn University of

Digital Integrated Circuit:
An Introduction
Theerayod Wiangtong
Electronic Department
Mahanakorn University of Technology
1
Outlines
• Introduction to Digital IC designs: History,
Evolutions, etc.
• Introduction to ASIC: CMOS IC designs
• Introduction to FPGA: Chips and Design Processs
2
Semiconductor: The Revolution
First transistor
Bell Labs, 1948
3
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
4
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
5
Intel Pentium (IV) processor
2001
42 M transistors
1.5 GHz operation
6
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
386
286
0.1
0.01
P6
Pentium® proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
7
Courtesy, Intel
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends (ITRS)
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
8
Courtesy, ITRS Roadmap
Technology on Semiconductor
9
Design Methodology
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Design Styles
•
•
•
•
Full-Custom Design
Standard Cell Design
Gate Array Design
Field Programmable Gate Array Design
(FPGA)
• … or mixtures of the above
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Full-Custom Design
• No rigid restrictions on
layout.
• More compact design.
• Longer design time.
• Hierarchical: chip 
clusters  units 
functional units.
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Standard Cell Design
• Rectangular cells of the
same height.
• Cell library (has 500 1200 cells).
• Cells placed in rows and
space between rolls are
called channels for routing.
• Feedthroughs
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Gate Array Design
• Each chip is prefabricated
with an array of identical
gates or cells.
• The chip is “customized”
by fabricating routing
layers on top.
• For example, MPGA
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Field Programmable Gate Array
• Chips are prefabricated with logic
blocks and interconnects.
• Logic and interconnects can be
programmed (erased and reprogrammed) by users. No
fabrication is needed.
• Interconnects are predefined wire
segments of fixed lengths with
switches in between.
• For example, FPGA, CPLD
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What is this course all about?
• Digital integrated circuit design
– Cell-based: ASIC design, Primitive component,
Combinational and Sequential circuits, Arithmetic,
interconnect, and memories.
– Array based: Programmable logic arrays. FPGA,
HDL, Design methodologies.
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The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
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ENIAC - The first electronic computer (1946)
ENIAC contained 17,468 vacuum tubes, 7,200 crystal
diodes, 1,500 relays, 70,000 resistors, 10,000 capacitors
and around 5 million hand-soldered joints. It weighed 30
short tons (27 t), was roughly 8.5 feet (2.6 m) by 3 feet
(0.91 m) by 80 feet (2.6 m by 0.9 m by 26 m), took up
680 square feet (63 m²), and consumed 150 kW of
power.[6] Input was possible from an IBM card reader,
and an IBM card punch was used for output
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Intel Pentium (IV) microprocessor
The Computer in 50
years later!
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Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
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Evolution in Complexity
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Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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Courtesy, Intel
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
386
286
0.1
0.01
P6
Pentium® proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
23
Courtesy, Intel
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
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Courtesy, Intel
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
25
Courtesy, Intel
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
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Courtesy, Intel
Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086 386
10
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
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Courtesy, Intel
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
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Courtesy, Intel
Challenges in Digital Design
•
•
•
•
•
•
“Microscopic Problems”
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Everything Looks a Little
Different
?
•
•
•
•
•
•
“Macroscopic Issues”
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.
…and There’s a Lot of Them!
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Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
D
n+
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Design Metrics
• How to evaluate performance of a digital circuit (gate,
block, …)?
–
–
–
–
–
–
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
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Cost of Integrated Circuits
• NRE (non-recurrent engineering) costs
– design time and effort, mask generation
– one-time cost factor
• Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
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NRE Cost is Increasing
33
Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
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Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
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Yield
No. of good chips per wafer
Y
100%
T otalnumber of chips per wafer
Wafercost
Die cost 
Dies per wafer Die yield
  wafer diameter/22   wafer diameter
Dies per wafer

die area
2  die area
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Some Examples
Chip
Metal
layers
Line
width
Wafer
cost
Def./
cm2
Area
mm2
Dies/w
afer
Yield
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC 601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
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Impact of
Technology Scaling
38
Goals of Technology Scaling
• Make things cheaper:
– Want to sell more functions (transistors) per chip for the
same money
– Build same products cheaper, sell the same part for
less money
– Price of a transistor has to be reduced
• But also want to be faster, smaller, lower power
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Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of Introduction
1999
Technology node [nm]
180
Supply [V]
1.5-1.8
Wiring levels
2000
2001
2004
2008
2011
2014
130
90
60
40
30
1.5-1.8
1.2-1.5
0.9-1.2
0.6-0.9
0.5-0.6
0.3-0.6
6-7
6-7
7
8
9
9-10
10
Max frequency
[GHz],Local-Global
1.2
1.6-1.4
2.1-1.6
3.5-2
7.1-2.5
11-3
14.9
-3.6
Max mP power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
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ITRS Technology Roadmap
41
Terminology
• ITRS: International Technology Roadmap for Semiconductors. It is
devised and intended for technology assessment only and is without
regard to any commercial considerations pertaining to individual
products or equipment
• DRAM Half-pitch: The common measure of the technology generation
of a chip. It is half the distance between cells in a dynamic RAM
memory chip. For example, in 2002, the DRAM half pitch has been
reduced to 130 nm (.13 micron).
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Half Pitch
DRAM ½ pitch
= DRAM metal pitch/2
MPU/ASIC M1 ½ pitch
= MPU/ASIC M1 pitch/2
Metal
pitch
Passivation
Dielectric
Wire
Etch Stop Layer
Via
Dielectric Capping Layer
Copper Conductor with
Barrier/Nucleation Layer
Global
Intermediate
Typical DRAM/MPU/ASIC
Metal Bit Line
Metal 1
Pre-Metal Dielectric
Tungsten Contact Plug
Metal 1 Pitch
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Technology Scaling: To preserve Moore’s
Law
Number of components per chip
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2010 Outlook
• Performance 2X/16 months
– 1 TIP (terra instructions/s)
– 30 GHz clock
• Size
– No of transistors: 2 Billion
– Die: 40*40 mm
• Power
– 10kW!!
– Leakage: 1/3 active Power
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Wafer Size
Past   Future
200mm/1990a
300mm/2001a
450mm/2012f
675mm/>2021f?
(125/150mm ~1981)
46
NRE Cost: Example
http://www.mosis.org/prices.html
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Some interesting questions
• What will cause this model to break?
• When will it break?
• Will the model gradually slow down?
–
–
–
–
–
–
Power and power density
Leakage
Process Variation
Delay
NRE Cost
Etc.
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Summary
• Digital integrated circuits have come a long way and
still have quite some potential left for the coming
decades.
• Some interesting challenges ahead
– Getting a clear perspective on the challenges and potential
solutions is the purpose of this book
• Understanding the design metrics that govern digital
design is crucial
– Cost, reliability, speed, power and energy dissipation
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QUESTIONS?
THANK YOU
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