Transcript Moore`s law - The School of Electrical Engineering and Computer

EE586
VLSI Design
Partha Pande
School of EECS
Washington State University
[email protected]
Lecture 1 (Introduction)
 Why
is designing
digital ICs different
today than it was
before?
 Will it change in
future?
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
ENIAC - The first electronic computer (1946)
The Transistor Revolution
First transistor
Bell Labs, 1948
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
Intel Pentium (IV) microprocessor
Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
Evolution in Complexity
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Courtesy, Intel
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8080
8008
4004
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
0.001
1970
1980
1990
Year
Courtesy, Intel
2000
2010
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
Courtesy, Intel
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
MOS Transistor Scaling
(1974 to present)
Scaling factor s=0.7 per node (0.5x per 2 nodes)
Metal pitch
Technology Node
set by 1/2 pitch
(interconnect)
Poly width
Gate length
(transistor)
Ideal Technology Scaling (constant field)
Quantity
Before Scaling
After Scaling
Channel Length
L
L’ = L * s
Channel Width
W
W’ = W * s
Gate Oxide thickness tox
t’ox = tox * s
Junction depth
xj
x’j = xj * s
Power Supply
Vdd
Vdd’ = Vdd * s
Threshold Voltage
Vth
V’th = Vth * s
Doping Density, p
n+
NA
ND
NA’ = NA / s
ND’ = ND / s
Challenges in Digital Design
 DSM
 1/DSM
“Macroscopic Issues”
“Microscopic Problems”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
?
…and There’s a Lot of Them!
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
Why Scaling?
Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …

 How to design chips with more and more functions?
 Design engineering population does not double every
two years…

Hence, a need for more efficient design methods
 Exploit different levels of abstraction
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
D
n+
Design Metrics
 How
to evaluate performance of a
digital circuit (gate, block, …)?






Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
Cost of Integrated Circuits

NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor

Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
NRE Cost is Increasing
Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
What about Interconnect
 Global
wires
 Non-scalable delay
 Delay exceeds one clock cycle
 Non-scalable interconnects
 Excessive power dissipation
 Non reliability in signal transmission
Emerging Interconnect Technologies
Three Dimensional
Integration
Optical Interconnects
Lower Latency
and Energy
Dissipation
Wireless/RF
Interconnects
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
 Some interesting challenges ahead

 Getting a clear perspective on the challenges and
potential solutions is the purpose of this course

Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy
dissipation
Course Structure
MOS Transistors
 MOS Inverter Circuits
 Static MOS Gate Circuits
 High-Speed CMOS Logic Design
 Transfer Gate and Dynamic Logic Design
 Semiconductor Memory Design
 Advanced Devices beyond CMOS

Course Structure
 Extensive
use of CAD tools
 Homework assignments
 One to two midterm exams and one
final exam
 Course Project
Suite of two courses EE 466/586 and
EE587 will cover various aspects
starting from circuits to systems
References

Textbook:
 CMOS VLSI Design, Weste and Harris, Fourth
Edition

Additional Reference:
 Analysis and Design of Digital Integrated Circuits In Deep Submicron Technology, Hodges, Jackson
and Saleh, McGraw-Hill, Third Edition, 2004.
 J. M. Rabaey, A. Chandrakasan, and B. Nikolic,
Digital Integrated Circuits: A Design Perspective.
Second Edition, Prentice Hall, 2003.

Important announcements will be posted in
the course website
 www.eecs.wsu.edu/~ee586