Transcript ECE Users Pages - Georgia Institute of Technology

ECE3055
Computer Architecture and
Operating Systems
Lecture 1 Introduction
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Institute of Technology
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Objectives  To Learn
 Core concepts of microprocessor architecture
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ISA (review of 2030)
Pipelining
Hazards
Cache/Memory hierarchy
Memory management
 Core concepts of operating systems
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Processes/threads
Protection
Resource Management
Scheduling
File System
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Course Information
 Web page: http://www.ece.gatech.edu/~leehs/ECE3055
 Will be constantly updated, so check it out regularly
 Prerequisite: ECE2031 Digital Design Lab
 Textbooks
 Patterson and Hennessey, Computer Organization &
Design: The Hardware/Software Interface (3rd
edition), Morgan Kaufmann, 2004. ISBN 1-55860604-1.
 Silberschatz, Galvin, and Gagne, Operating System
Concepts with Java (6th edition), John Wiley, 2004.
ISBN 0471489050.
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Grading Policy
 5 Programming Assignments: 35% (5, 10, 10, 5, 5%)
 Individual work, no collaboration
 Due in the first 5 min before class starts
 No late turn-in will ever be accepted
 Exams
 3 in-class exams: 45% (15% each, dates TBD)
 Final: 20% (date on Oscar)
 Final Grade is relative to your peer in class
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Part I: Patterson & Hennessy book
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Introduction
 Rapidly changing field:
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vacuum tube -> transistor -> IC -> VLSI (see section 1.4)
doubling every 1.5 years:
memory capacity
processor speed (Due to advances in technology and organization)
 Things you’ll be learning:
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how computers work, a basic foundation
how to analyze their performance (or how not to!)
issues affecting modern processors (caches, pipelines)
 Why learn this stuff?
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you want to call yourself a “computer scientist”
you want to build software people use (need performance)
you need to make a purchasing decision or offer “expert” advice
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Moore’s Law
P4 Extreme Ed.
178 millions w/ 2MB L3
IBM latest POWER5 has
276 million transistors
Intel Dual-Core Xeon (P4-based
Tulsa) w/ 16MB unified L3:
1.328 billion, 2006
2,250
Core 2 Duo (Conroe)
291 millions, July
2006
42 millions
Exponential growth
Transistor count will be doubled every 18 months
 Gordon Moore, Intel co-founder
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Integrated Circuits Capacity
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Feature Size
We are currently at 0.09µm and moving towards 0.065µm
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Average Transistor Cost Per Year
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What is a computer?
 Components:
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Processor(s)
Co-processors (graphics, security)
Memory (disk drives, DRAM, SRAM, CD/DVD)
input (mouse, keyboard, mic)
output (display, printer)
network
 Our primary focus: the processor (datapath and control)
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implemented using millions of transistors
Impossible to understand by looking at each transistor
We need...
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Abstraction
High Level
Language
main() {
int i,b,c,a[10];
for (i=0; i<10; i++)…
a[2] = b + c*i;
}
Compiler
ISA
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lw r2, mem[r7]
add r3, r4, r2
st
r3, mem[r8]
 Delving into the depths
reveals more information
 An abstraction omits unneeded
detail,
helps us cope with complexity
 What are some of the details
that appear in these familiar
abstractions?
Assembler
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A Typical PC System Architecture
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A Typical PC Motherboard (D975XBX)
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A Typical PC Motherboard (D975XBX)
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Instruction Set Architecture
 A very important abstraction
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interface between hardware and low-level software
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standardizes instructions, machine language bit patterns, etc.
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advantage: different implementations of the same architecture
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disadvantage: sometimes prevents using new innovations
True or False: Binary compatibility is extraordinarily important?
 Modern instruction set architectures:
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80x86 (aka iA32), PowerPC (e.g. G4, G5)
Xscale, ARM, MIPS
Intel/HP EPIC (iA64), AMD64, Intel’s EM64T, SPARC, HP PA-RISC,
DEC/Compaq/HP Alpha
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Where we are headed
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Performance issues
A specific instruction set architecture
Arithmetic and how to build an ALU
Constructing a processor to execute our instructions
Pipelining to improve performance
 Memory: caches and virtual memory
 I/O
 I will try to cover as much as possible, but do not
forget we have another half of the semester for OS
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