Transcript Document

What this lecture is all about?

Introduction to digital integrated circuits.
 CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.

What will you learn?
 Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability
1
Digital Integrated Circuits
Introduction: Issues in digital design
 The CMOS inverter
 Combinational logic structures
 Sequential logic gates
 Design methodologies
 Interconnect: R, L and C
 Timing
 Arithmetic building blocks
 Memories and array structures

2
Introduction
 Why
is designing
digital ICs different
today than it was
before?
 Will it change in
future?
3
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
4
ENIAC - The first electronic computer (1946)
5
The Transistor Revolution
First transistor
Bell Labs, 1948
6
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
7
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
8
Intel Pentium (IV) microprocessor
9
Why VLSI?
 Integration
improves the design:
 lower parasitics = higher speed;
 lower power;
 physically smaller.
 Integration
reduces manufacturing cost(almost) no manual assembly.
10
VLSI and you
 Microprocessors:
 personal computers;
 microcontrollers.
 DRAM/SRAM.
 Special-purpose
processors.
11
Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
12
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
13
Evolution in Complexity
14
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Courtesy, Intel
15
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8080
8008
4004
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
0.001
1970
1980
1990
Year
Courtesy, Intel
2000
2010
16
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
17
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
18
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
19
Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
20
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
Courtesy, Intel
21
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
22
Challenges in Digital Design
 DSM
 1/DSM
“Macroscopic Issues”
“Microscopic Problems”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
?
…and There’s a Lot of Them!
23
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
24
Why Scaling?
Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …

 How to design chips with more and more functions?
 Design engineering population does not double every
two years…

Hence, a need for more efficient design methods
 Exploit different levels of abstraction
25
Challenges in VLSI design
 Multiple
levels of abstraction: transistors
to CPUs.
 Multiple and conflicting constraints: low
cost and high performance are often at
odds.
 Short design time: Late products are
often irrelevant.
26
Dealing with complexity
 Divide-and-conquer:
limit the number of
components you deal with at any one
time.
 Group several components into larger
components:




transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
27
Hierarchical name
 Interior
view of a component:
 components and wires that make it up.
 Exterior
view of a component = type:
 body;
 pins.
cout
a
b
Full
adder
sum
cin
28
Instantiating component types
 Each
instance has its own name:
 add1 (type full adder)
 add2 (type full adder).
 Each
instance is a separate copy of the
type:
cout Add2.a
Add1.a
a Add1(Full
adder)
b
sum
a Add2(Full
adder)
b
cin
sum
cin
29
Net lists and component lists

Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out

Component list:
top: in1=net1
n1=topin1 n2=topin2
n3=topine out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2
xin3=botin1 B=net2
out=net3
i2: in=net3 out=outnet
30
Component hierarchy
top
i1
xxx
i2
31
Hierarchical names
 Typical
hierarchical name:
 top/i1.foo
component pin
32
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
D
n+
33
Layout and its abstractions
 Layout
for dynamic latch:
34
Stick diagram
35
Transistor schematic
36
Mixed schematic
inverter
37
Levels of abstraction
 Specification:
function, cost, etc.
 Architecture: large blocks.
 Logic: gates + registers.
 Circuits: transistor sizes for speed,
power.
 Layout: determines parasitics.
38
Circuit abstraction
 Continuous
voltages and time:
39
Digital abstraction
 Discrete
levels, discrete time:
40
Register-transfer abstraction
 Abstract
components, abstract data
types:
0010
+
0001
+
0111
0100
41
Top-down vs. bottom-up design
 Top-down
design adds functional detail.
 Create lower levels of abstraction from
upper levels.
 Bottom-up
design creates abstractions
from low-level behavior.
 Good design needs both top-down and
bottom-up efforts.
42
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
cost
Literals,
logic depth
transistors
circuit
nanoseconds
rectangles
layout
microns
43
Design Metrics
 How
to evaluate performance of a
digital circuit (gate, block, …)?






Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
44
Cost factors in ICs
 For
large-volume ICs:
 packaging is largest cost;
 testing is second-largest cost.
 For
low-volume ICs, design costs may
swamp all manufacturing costs.
45
Cost of Integrated Circuits

NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor

Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
46
NRE Cost is Increasing
47
Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
48
Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
49
2012
Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer 

die area
2  die area
50
Defects
 defects per unit area  die area 
die yield  1 





 is approximately 3
die cost  f (die area) 4
51
Some Examples (1994)
Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/ Yield
cm2 mm2 wafer
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
52
Reliability―
Noise in Digital Integrated Circuits
v(t)
V DD
i(t)
Inductive coupling
Capacitive coupling
Power and ground
noise
53
DC Operation
Voltage Transfer Characteristic
V(y)
V
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
f
OH
V(y)=V(x)
VM Switching Threshold
V OL
V OL
V
OH
V(x)
Nominal Voltage Levels
54
Mapping between analog and digital signals
V
“ 1”
V
OH
V
V
IH
out
Slope = -1
OH
Undefined
Region
V
“ 0”
V
Slope = -1
IL
V
OL
OL
V
IL
V
IH
V
in
55
Definition of Noise Margins
"1"
V
OH
Noise margin high
NM H
V
IH
Undefined
Region
V
OL
NM L
V
IL
Noise margin low
"0"
Gate Output
Gate Input
56
Noise Budget
 Allocates
gross noise margin to
expected sources of noise
 Sources: supply noise, cross talk,
interference, offset
 Differentiate between fixed and
proportional noise sources
57
Key Reliability Properties

Absolute noise margin values are deceptive
 a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)

Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
58
Regenerative Property
Regenerative
Non-Regenerative
59
Regenerative Property
v0
v1
v2
v3
v4
v5
v6
A chain of inverters
Simulated response
60
Fan-in and Fan-out
N
Fan-out N
M
Fan-in M
61
The Ideal Gate
V out
Ri = 
Ro = 0
Fanout = 
NMH = NML = VDD/2
g=
V in
62
An Old-time Inverter
5.0
4.0
NM L
3.0
(V)
2.0
out
V
VM
NM H
1.0
0.0
1.0
2.0
3.0
V in (V)
4.0
5.0
63
Delay Definitions
64
Ring Oscillator
T = 2  tp  N
65
A First-Order RC Network
R
vin
vout
C
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter
66
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave  
p(t )dt 
isupply t dt

t
T t
T
67
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =
quality metric of gate = E  tp
68
A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS
A1
NETWORK
vAinN
NMOS
i
vout supply
CVLout
CL
NETWORK
T
E
01
=  P  t  dt = V  i
t dt = V
dd sup ply 
dd
0
0
T
E
Vdd
T
T
= P
t dt =  V
i
t dt =
ca p
cap  
out ca p 
0
0

0
C dV
= C V 2
L out
L
dd
Vdd
1
2
-C  V
 C L Vout dVout = -dd
2 L
0
69
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
 Some interesting challenges ahead

 Getting a clear perspective on the challenges and
potential solutions is the purpose of this book

Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy
dissipation
70