Transcript Thin Film Overview

EMT362: Microelectronic Fabrication
Contact Technology For
The VLSI Process
Ramzan Mat Ayub
School of Microelectronic Engineering
School of Microelectronic Engineering
Lecture Objectives
• Able to identify ALL back-end process modules from wafer cross section.
• Understand the important of ohmic contact and able to describe step
by step ohmic contact formation.
• Understand the importance of contact resistance monitoring,
extraction method and test structure.
• Understand the application of diffusion barrier layer
• Able to describe silicide and salicide processes.
School of Microelectronic Engineering
Standard CMOS Process Flow
Main Process Modules (CMOS 1P2M 3.3V)
1.
Wells Formation
2. Active Area Definition
3. Device Isolation (LOCOS)
4. Vt Adjust
5. Polygate Definition
6. Source & Drain Formation
7. Pre Metal Dielectrics Deposition (PMD)
8. Contact Definition
9. Metal-1 Deposition & Patterning
10. Inter-Metal Dielectrics Deposition (IMD)
11. Via Definition
12. Metal-2 Deposition & Patterning
13. Passivation
14. Pad Definition
FRONT END PROCESS
(creating an electrically isolated devices)
BACK END PROCESS
(connecting the devices to form the desired
circuit function.)
Full integration may require 300-500 process steps
School of Microelectronic Engineering
Back-end Process Overview
School of Microelectronic Engineering
56. Resist Removal
Test Insert
and
Scribe-line
Capacitor
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
N-Well
NMOS
Equipment
a. Strip resist
Plasma O2 ,
Etch stop :
Endpoint/time
Matrix 106
(AS101)
b. Wet strip
H2SO4 : H2SO4:H2O2
(3 : 1)
10’, 130C
Verteq 1083
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
i. Visual inspection (refer
C10ETAS101OP).
ii. Weekly ash rate tests.
iii. Weekly particle tests.
Weelly particle test
Purpose
Remove photoresist.
Removes remaining traces of
photoresist.
57. BPSG Deposition : To isolate metal 1 from polysilicon lines and gates
Test Insert
and
Scribe-line
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
N-Well
NMOS
Sequence
Operation
Equipment
USG
deposition
TEOS, O2
P5000(ET102)
BPSG
deposition
TEOS, O2
TMP, TMB
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
100 nm
750 nm ± 2%
4 wt% B
4 wt% P
Weekly thickness,
uniformity tests
Weekly Particle Test
B/P content tests
Capacitor
Purpose
Undoped oxide to act as barrier
for Boron/Phosphorus outdiffusion
Dielectric layer can be reflowed
at low temperatures
58. Reflow
Test Insert
and
Scribe-line
BPSG
Capacitor
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Reflow
N-Well
NMOS
Operation
Equipment
30’ 900C
ASM SB/T1
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
Purpose
To form a more planar layer
of BPSG.
To anneal S/D BF2 implant
59. Lithography Contact
Test Insert
and
Scribe-line
Resist
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Anneal
a. Resist coat
b. Exposure
c. Development
Operation
800 C , 15 ‘, N2
HMDS: 45s, AZ
7212 DS
4.1krpm
SB: 115C
Reticle layer N1
300 msec
PEB, Develope
45s, HB
N-Well
NMOS
Equipment
Specification
Process Control
ASM SB/T1
SVG 88
Capacitor
Purpose
To prepare wafer surface for better
priming
1.2  0.01
um
NSR
2005i8A
SVG 88
thickness SPC chart
To coat a layer of
photosensitive resist onto
wafer substrate
phototest
To transfer pattern from reticle
onto resist layer
To create reticle pattern on
resist layer upon development
To ensure the above operations
and equipments are under
control
To ensure stepper alignment is
under control
d. CD
measurement
Metra
2150m
1.60.15
um
3 wfrs/lot, 5 pts measurements,
turning fork structure, SPC chart
e. Overlay
measurement
Metra
2150m
300 nm
3 wfrs/lot, 5 pts measurements,
box-in-box structure, SPC chart,
PM equipment calibration
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
60. Contact Etch
Test Insert
and
Scribe-line
Resist
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
N-Well
NMOS
Sequence
Operation
a. DUV cure
170 C, 35s
Fusion 150 PC
b. Etch USG
100 nm + BPSG
650 nm
RIE CHF3, CF4, NF3,
Ar
AMAT P5000
(ET102)
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Equipment
Specification
i.
Etch through 40
nm of silicon
ii. Profile
anisotropic > 87
iii. CD loss < 0.025
m/side
Process Control
i.
Run trial etch before
etching the whole lot.
ii. Visual inspection
( refer to C10ETET1OP).
Capacitor
Purpose
Harden the photoresist to
prevent resist reticulation.
Open contact hole for metal
1 and source/drain.
61. Resist Coat, Backside Etch, Resist Removal
Test Insert
and
Scribe-line
Resist
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
N-Well
NMOS
Specification
SVG 88/
NanoSpec
Oven
1.2  0.01 um
thickness SPC
chart
1b. Hardbake
HMDS:45s, AZ
7212 DS,
115C, 45min
To protect the front-side of
substrate during etch
To harden the resist
2. Backside
etch
isotropic etch
NF3, He, O2
Matrix 303
E.R. > 7000
A/min.
Backside rinse test.
Weekly etchrate
test.
Remove polysilicon and oxide
on backside of wafer.
3a. Strip resist
Plasma O2
Matrix 106
Remove photoresist
3b. Wet strip
H2SO4:H2O2(3:1)
10’ 130C
Verteq 1083
Removes remaining traces of
photoresist
School of Microelectronic Engineering
Process Control
Capacitor
Equipment
1a. Resist coat
Operation
Arsenic Implant
As+ S/D Implant
Purpose
62. Titanium/Titanium Nitride Deposition
Test Insert
and
Scribe-line
Ti/TiN
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
N-Well
NMOS
Equipment
1. Contact
cleaning
HF 1% dip 60 s
Verteq 1083
2.a. Titanium
deposition
2.b. TiN
deposition
400 C, 3.5 mT
Ar
400 C, 3.5 mT
Ar/N2
Endura
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
20 nm ± 5%
80 nm ± 5%
Capacitor
Process Control
Purpose
etch rate test
etch native oxide in the contacts
resistivity, uniformity
and reflectivity tests
 provide silicide formation
 reduce contact resistance
 act as a barrier layer to prevent
spiking
63. Anneal
Test Insert
and
Scribe-line
Ti/TiN
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Anneal
N-Well
NMOS
Operation
Equipment
700 C, N2 , 1 min
AST RTA
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
Resistivity tests
Oxidation Test
Capacitor
Purpose
to form TiSi for lower contact
resistance
64. Metal 1 Deposition
Test Insert
and
Scribe-line
TiN ARC Layer
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
N-Well
NMOS
Operation
Equipment
1.a. AlSiCu
deposition
175 C, 3.2 mT
Ar
Endura
1.b. TiN
deposition
400 C, 3.5 mT
Ar/N2
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
500 nm ± 5%
50 nm ± 10%
Process Control
Resistivity ,uniformity
and reflectivity tests
Weekly Particle tests
Capacitor
Purpose
to form metal-1 interconnection
to act as an ARC layer for the
subsequent photolithography
step
65. Lithography Metal-1
Test Insert
and
Scribe-line
TiN ARC Layer
Resist
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
Arsenic Implant
As+ S/D Implant
P-Well
PMOS
N-Well
NMOS
Capacitor
Sequence
Operation
a. Resist coat
HMDS: 45s,
AZ 7212 DS
4.1krpm,
SB:115C
Reticle layer
G1, 300 msec
PEB, Develope
45s, HB
b. Exposure
c. Development
d. CD
measuremen
t
e. Overlay
measuremen
t
Program ___
School of Microelectronic Engineering
Equipment
SVG 88
Specification
1.2 
0.01
um
NSR2005i
8A
SVG 88
Process Control
Purpose
thickness SPC chart
To coat a layer of
photosensitive resist onto
wafer substrate
phototest
To transfer pattern from
reticle onto resist layer
To create reticle pattern on
resist layer upon
development
To ensure the above
operations and equipments
are under control
To ensure stepper alignment
is under control
Metra
2150m
1.60.
1 um
3 wfrs/lot, 5 pts measurements,
turning fork structure, SPC chart
Metra
2150m
200
nm
3 wfrs/lot, 5 pts measurements, boxin-box structure, SPC chart, PM
equipment calibration
66. Metal-1 Etch/Resist Removal
Test Insert
and
Scribe-line
TiN ARC Layer
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
N-Well
NMOS
Operation
Equipment
a. DUV cure
170 C, 35 s
Fusion 150 PC
(DU101)
b.Etch metal
stack 650nm
RIE BCL3, CL2, CF4,
N2, SF6
endpoint + 75% OE
AMAT P5000
(ET101)
i.
c. Strip resist
and passivation
Plasma O2, N2, H2O
AMAT P5000
(ET101)
corrosion resistance
after resist strip : 24hrs.
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
Capacitor
Purpose
Harden the photoresist to
prevent resist reticulation.
CD loss < 0.05
m/side
ii. Profile Anisotropic
> 87
iii. Oxide (BPSG) loss
< 1000 A
visual inspection
(refer to
C10ETT10P)
Pattern the first metal
interconnection layer.
Remove photoresist and
passivate metal layer from
corrosion.
66. Metal-1 Etch / Capacitor
Test Insert
and
Scribe-line
Metal 1
BPSG
FOX
FOX
FOX
LDD
N-Well
P-Well
PMOS
Sequence
Arsenic Implant
As+ S/D Implant
NMOS
Operation
Equipment
a. DUV cure
170 C, 35 min
Fusion 150 PC
(DU101)
b.Etch metal
stack 650nm
RIE BCL3, CL2, CF4,
N2, SF6
endpoint + 75% OE
AMAT P5000
(ET101)
ii) Strip resist
and passivation
Plasma O2, N2, H2O
AMAT P5000
(ET101)
School of Microelectronic Engineering
Specification
Capacitor
Process Control
Purpose
Harden the photoresist to
prevent resis t reticulation.
i.
CD loss < 0.05
m/side
ii. Profile Anisotropic
> 87
iii. Oxide (BPSG) loss
< 1000 Å
iv. Corrosion
resistance 72 hrs.
Pattern the first metal
interconnection layer.
Remove photoresist and
passivate metal layer from
corrosion.
67. Solvent Strip
Test Insert
and
Scribe-line
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Resist Strip
N-Well
NMOS
Operation
Equipment
EKC 265 (65C)
IPA, DI H2O
Semitool
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
metal
corrosion
resistance :
7 days
Process Control
Weekly Particle Test
Capacitor
Purpose
To remove complex polymers
and photoresist
68. Parameter Test 1
Test Insert
and
Scribe-line
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Parameter
Test
7200
Operation
5000
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
N-Well
NMOS
Equipment
PT101
Specification
C10PDPT10P
Process Control
Capacitor
Purpose
To extract electrical parameters
of basic devices such as
transistors, diodes, capacitors,
etc. The extracted parameters are
used to monitor fabrication
processes.
This step also serves as a first
wafer sort station.
69. IMD-1 and Planarisation
Test Insert
and
Scribe-line
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
N-Well
NMOS
Operation
Equipment
a. Clean C1
surfactant 10’
Verteq
b. Solvent strip
c.1. Deposit
USG 700 nm
EKC 265, 65C
PECVD TEOS, O2
Semitool
AMAT P5000
(ET102)
Target thickness
700nm
c.2. Sputter
Etch 120 nm
RIE Ar
AMAT P5000
(ET102)
Remaining thickness
580nm.
c.3. Deposit
USG 2500 nm
PECVD TEOS, O2
AMAT P5000
(ET102)
Total thickness 3080
nm.
Weekly deposition rate
test.
d. Etchback
RIE O2, CF4, Ar, He
AMAT P5000
(ET102)
Final thickness 900
nm.
Measure thickness
using Nanospec.
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
Capacitor
Purpose
Remove contamination and
particles
Weekly deposition rate
test.
Taper the edges.
70. Lithography Via-Contact
Test Insert
and
Scribe-line
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
a. Resist coat
HMDS: 45s,
AZ 7212 DS
4.1krpm,
SB:115C
Reticle layer
G1, 300 msec
PEB, Develope
45s, HB
b. Exposure
c. Development
d. CD
measurement
e. Overlay
measurement
Program ___
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
N-Well
NMOS
Equipment
SVG 88
Specification
1.2 
0.01
um
NSR2005i
8A
SVG 88
Process Control
Capacitor
Purpose
thickness SPC chart
To coat a layer of
photosensitive resist onto
wafer substrate
phototest
To transfer pattern from
reticle onto resist layer
To create reticle pattern on
resist layer upon development
To ensure the above
operations and equipments
are under control
To ensure stepper alignment
is under control
Metra
2150m
1.60.
1 um
3 wfrs/lot, 5 pts measurements,
turning fork structure, SPC chart
Metra
2150m
200
nm
3 wfrs/lot, 5 pts measurements, boxin-box structure, SPC chart, PM
equipment calibration
71. Via-Contact Etch
Test Insert
and
Scribe-line
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
Arsenic Implant
N-Well
NMOS
Equipment
a. DUV cure
160 C, 35 s
Fusion 150 PC (
b. Etch USG
900 nm
RIE Ar, CHF3, CF4,
O2
AMAT P5000
(ET102)
School of Microelectronic Engineering
As+ S/D Implant
Specification
Process Control
Capacitor
Purpose
Harden the photoresist to
prevent resist reticulation.
i. Etch through 50
nm of TiN ARC.
ii. Profile >87.
iii. CD loss < 0.05
m/feature.
Visual inspection
( refer to C10ETET1OP).
Open via hole for metal 1
and 2 interconnection.
72. Resist Removal
Test Insert
and
Scribe-line
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
As+ S/D Implant
PMOS
Sequence
Operation
Arsenic Implant
N-Well
NMOS
Equipment
Specification
Process Control
Purpose
Capacitor
a. Strip resist
Plasma O2.
Etch stop:
Endpoint/time
Matrix 106
(AS101)
i.
Visual inspection (refer
C10ETAS101OP).
ii. Weekly ash rate tests.
iii. Weekly particle tests.
Remove photoresist.
b. Solvent strip
EKC 265 (65C),
IPA, DI H2O
Semitool
Weekly particle tests
Remove complex polymers
School of Microelectronic Engineering
73. Metal 2 Deposition
TiN ARC-Layer
Test Insert
and
Scribe-line
AlSiCu
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
AlSiCu
deposition
Equipment
175 C, 3.2 mT
Ar
Endura
School of Microelectronic Engineering
N-Well
NMOS
Operation
TiN deposition 400C, 3.5 mT
Ar/N2
Arsenic Implant
As+ S/D Implant
Specification
1 m ± 5%
50 nm ± 10%
Process Control
Resistivity,
uniformity tests
Weekly Particle test
Weekly reflectivity test
Resistivity, uniformity
and reflectivity tests.
Capacitor
Purpose
to form metal-2 interconnection
to act as an ARC layer for the
subsequent photolithography step
74. Lithograpy Metal 2
Test Insert
and
Scribe-line
AlSiCu
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
a. Resist coat
HMDS: 45s,
AZ 7212 DS
4.1krpm,
SB:115C
Reticle layer
G1, 300 msec
PEB, Develope
45s, HB
b. Exposure
c. Development
d. CD
measurement
e. Overlay
measurement
Program ___
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
N-Well
NMOS
Equipment
SVG 88
Specification
1.2 
0.01
um
NSR2005i
8A
SVG 88
Process Control
Capacitor
Purpose
thickness SPC chart
To coat a layer of
photosensitive resist onto
wafer substrate
phototest
To transfer pattern from
reticle onto resist layer
To create reticle pattern on
resist layer upon development
To ensure the above
operations and equipments
are under control
To ensure stepper alignment
is under control
Metra
2150m
1.60.
1 um
3 wfrs/lot, 5 pts measurements,
turning fork structure, SPC chart
Metra
2150m
200
nm
3 wfrs/lot, 5 pts measurements, boxin-box structure, SPC chart, PM
equipment calibration
75. Metal 2 Etch / Resist Removal
Test Insert
and
Scribe-line
Metal 2
Planarisation
AlSiCu
BPSG
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Operation
Arsenic Implant
N-Well
NMOS
Equipment
a. DUV cure
160 C, 35 s
Fusion 150 PC
(DU101)
b. Etch Metal 2
RIE Bcl3, Cl2, CF4,
N2, SF6
AMAT P5000
(ET101)
School of Microelectronic Engineering
As+ S/D Implant
Specification
Process Control
Capacitor
Purpose
Harden the photoresist to
prevent resist reticulation.
i. CD loss < 0.05
um/side
ii. Profile >87.
iii. Oxide loss
(USG)<1000A
Visual inspection
( refer to C10ETET1OP).
Pattern the 2nd
interconnection layer
76. Solvent Strip
Test Insert
and
Scribe-line
Metal 2
Planarisation
AlSiCu
BPSG
FOX
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Sequence
Resist Strip
N-Well
NMOS
Operation
Equipment
EKC 265 (65C)
IPA, DI H2O
Semitool
School of Microelectronic Engineering
Arsenic Implant
As+ S/D Implant
Specification
Process Control
Weekly Particle Test
Capacitor
Purpose
To remove complex polymers
and photoresist
77. Passivation
Test Insert
and
Scribe-line
Metal 2
Passivation
Planarisation
AlSiCu
BPSG
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Arsenic Implant
As+ S/D Implant
N-Well
NMOS
P+ Substrate
Sequence
PSG
deposition
Operation
Equipment
PECVD TEOS,
O2, TMP
P5000 ETI 02
School of Microelectronic Engineering
Specification
750 ± 35 nm
2 wt% P
Process Control
Weekly etchrate test
Weekly thickness,
uniformity tests
Weekly P-content test
Purpose
Protective overcoat
Capacitor
78. Lithography Bond Pads
Resist
Passivation
Metal 2
Planarisation
Metal 1
BPSG
Field Oxide
Sequence
Operation
a. Resist coat
HMDS: 45s,
AZ 7212 DS
4.1krpm,
SB:115C
Reticle layer
G1, 300 msec
PEB, Develope
45s, HB
b. Exposure
c. Development
d. CD
measurement
e. Overlay
measurement
Program ___
School of Microelectronic Engineering
Equipment
SVG 88
Specification
1.2 
0.01
um
NSR2005i
8A
SVG 88
Process Control
Purpose
thickness SPC chart
To coat a layer of
photosensitive resist onto
wafer substrate
phototest
To transfer pattern from
reticle onto resist layer
To create reticle pattern on
resist layer upon development
To ensure the above
operations and equipments
are under control
To ensure stepper alignment
is under control
Metra
2150m
1.60.
1 um
3 wfrs/lot, 5 pts measurements,
turning fork structure, SPC chart
Metra
2150m
200
nm
3 wfrs/lot, 5 pts measurements, boxin-box structure, SPC chart, PM
equipment calibration
79. Passivation Etch
Resist
Resist
Bond Pad opening
Passivation
Metal 2
Planarisation
Metal 1
BPSG
Field Oxide
Silicon Substrate
Sequence
Operation
Equipment
a. DUV cure
160  C, 83 s
Fusion 150
PC (DU101)
b. Etch PSG
750 nm
RIE
Ar/CHF3/CF4/O2
AMAT P5000
(ET102)
School of Microelectronic Engineering
Specification
i. Etch through
50 nm of TiN
ARC.
Process Control
i. Visual inspection
ii. (refer to
C10ETET1OP).
Purpose
Harden the photoresist
to prevent resist
reticulation.
Open pads for probing
and bonding.
80. Resist Removal / Solvent Strip
Resist
Bond Pad opening
Passivation
Metal 2
Planarisation
Metal 1
BPSG
Field Oxide
Silicon Substrate
Sequence
Operation
Equipment
Specification
Process Control
Purpose
a. Strip resist
Plasma O2,
Etch stop:
Endpoint/time
Matrix 106
(AS101)
i. Visual inspection (refer
C10ETAS101OP).
ii. Weekly ash rate tests.
iii. Weekly particle tests.
Remove photoresist.
b. Solvent strip
EKC 265 (65)
IPA, DI H2O
Semitool
Weekly particle tests
Remove complex polymers
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81. Anneal
Resist
Bond Pad opening
Passivation
Metal 2
Planarisation
Metal 1
BPSG
Field Oxide
Silicon Substrate
Sequence
Anneal
Operation
440C, 10 min
forming gas
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Equipment
ASM SA/T4
Specification
Process Control
Purpose
Weekly particle test
to improve contact resistance,
anneal radiation damage and H2 sat
saturation of dangling bonds
82. PATMOS / Final Test
Test Insert
and
Scribe-line
Metal 2
Passivation
Planarisation
AlSiCu
BPSG
Spacer
FOX
FOX
LDD
BF2 S/D Implant
N-Well
P-Well
PMOS
Arsenic Implant
As+ S/D Implant
N-Well
NMOS
Capacitor
P+ Substrate
Sequence
Operation
Equipment
Specification
Final
parametric test
8600
5000
PT101
C10PDPT10P
Functional test
8700
5001
FT101
C10PDFT10P
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Process Control
Lot and wafer yield
Purpose
To extract electrical parameters of
basic devices such as transistors,
diodes, capacitors, etc. The
extracted parameters are used to
monitor fab processes.
To classify chips found in a fully
fabricated wafer according to its
functionality.
THE NEED FOR CONTACT
 WHEN ICs ARE FABRICATED, ISOLATED ACTIVE-DEVICE REGIONS ARE
CREATED WITHIN THE SINGLE-CRYSTAL SUBSTRATE.
 THE TECHNOLOGY USED TO CONNECT THESE ISOLATED DEVICES
THROUGH SPECIFIC ELECTRICAL PATHS EMPLOYS HIGH-CONDUCTIVITY,
THIN FILM CONDUCTOR MATERIALS FABRICATED ABOVE THE SIO2
INSULATOR THAT COVERS THE SILICON SURFACE.
 WHEREVER A CONNECTION IS NEEDED BETWEEN A CONDUCTOR FILM
AND THE SILICON SUBSTRATE, AN OPENING IN THE SIO2 MUST BE
PROVIDED TO ALLOW SUCH CONTACT TO OCCUR.
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METAL
GATE
PMD
Xj
Rac
Rco
Rsh
Rsp
 In MOSFET, current enters the contact perpendicular to the wafer surface, then
travels parallel to the surface to reach channel.
 The parasitic series resistance, RS of the current path from the contact to the edge
of the channel can be modeled as;
RS = Rco + Rsh + Rsp + Rac
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Where;
Rco – contact resistance between the metal and the S/D region
Rsh – sheet resistance of S/D regions
Rsp – resistance due to current crowding effect near the channel end of the source
Rac – accumulation layer resistance
Rco need to be accurately determined !
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THEORY OF METAL-SEMICONDUCTOR CONTACT
V
V
V
Ideal ohmic contact
I
I
I
Rectifying contact
Low-resistance ohmic
contact
 Ideal non-rectifying contacts would exhibit no resistance to the flow of current in
both directions.
 In general, metal-semiconductor contacts tend to exhibit non-ohmic I-V (due to the
work-function different of metal and semiconductor, potential energy barrier exist
between metal-semiconductor at thermal equilibrium). For e.g. Metal-n type S/C
potential barrier is 0.5V.
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Energy band diagram of metal-semiconductor contact
potential barrier
vacuum level
qΦm
qΦs
EF
e
Ec
EF
e
EF
e
e
Ev
metal
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n-type s/conductor
Rectifying contact
Ec
 However, it is still possible to fabricate metal - s/c contacts with I-V characteristics
that approach those of ideal case. This actual contact is referred as low-resistance
ohmic contact.
 Surface concentration in silicon is high, ND > 1019 cm-3
 Contact sintering (furnace anneal ~450ºC after metal deposition)
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SPECIFIC CONTACT RESISTIVITY, ρc
 PHYSICAL PARAMETERS THAT CHARACTERIZE THE INTERFACE
RESISTIVITY OF METAL – S/C CONTACT.
 THE ρc DESCRIBES THE INCREMENTAL RESISTANCE OF AN
INFINITELY SMALL AREA OF INTERFACE I.E THE INTERFACE
QUALITY.
 UNIT -cm2
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SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION
GATE
A – area of contact interface
Assume the current density over the entire area A is uniform;
ρc = Rk / A
Where Rk is V/I
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V
SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION
 Three most commonly used structures
 Cross-bridge Kelvin Resistor – CBKR
 Contact-end resistor – CER
 Transmission line tap resistor - TLTR
In all of these structures,
 a specific current is sourced from the diffusion level up to metal level through the
contact window.
 a voltage is measured between the two levels using two other terminals.
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CROSS-BRIDGE KELVIN RESISTOR
metal
2
1
L
ℓ
3
δ
diffusion
4
I
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L
PROCEDURE FOR EXTRACTING ρc FROM CBKR
1.
2.
3.
4.
5.
6.
7.
8.
9.
2 sets of CBKR test structures of varying contact sizes, ℓ
varying in length between 1 to 25 um, with at least 2 different
δ for each set of test structures.
The diffused region under the contacts for CBKR should be
fabricated to closely emulate the actual junctions to be built
in the actual devices. Normally both contacts on p+ and n+ need
to be built. The sheet resistance(ρsh) of diffused layers is to be measured.
After test structures have been fabricated, the value of Kelvin contact
resistance, Rk = V/I, of each contact is measured.
The value of log10 (Rk/ ρsh) is calculated for each contact.
The value of log10 (ℓ/δ ) is calculated for each contact.
The values of log10 (Rk/ ρsh) versus log10 (ℓ/δ ) are plotted for every set of different δ
Two value of y = ℓt / δ could be extracted from the curves where ℓt is the transfer length and
defined as ℓt = √ ρc/ρsh (ℓt is effective length of current crowding effect)
Since the δ values are known, ℓt can be found from ℓt = y δ
Since ℓt = √ ρc/ρsh , ρc is found from ρc = ℓt2 ρsh
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δ
ℓ
SPECIFIC CONTACT RESISTIVITIES OF VARIOUS METAL-SI CONTACTS
METAL-SI
AlSi to n+ Si
AlSi-TiN to n+ Si
AlSi-TiN to p+ Si
CVD W to n+ Si
Al-Ti:W – TiSi2 to p+ Si
Al-Ti:W – TiSi2 to n+ Si
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ρc (-m2)
15
1.0
20
11
60-80
13-25
CONTACT CHAIN FOR RCO MONITORING
 Generally, accurate value of Rco cannot be extracted from resistance data obtained from simple contact
chain structure.
 However, these kinds of contact chains are useful to provide rapid monitoring of the contact-fabrication
process.
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diffused region
metal
contact
PAD 1
PAD 2
PMD
n+
n+
P-substrate
R12 = V12 / I12
Rco = R12 / number of contact
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n+
BASIC PROCESS SEQUENCE OF CONVENTIONAL OHMIC-CONTACT
 Creation of heavily doped regions (n+ or p+)
 A window is etched in the oxide (contact hole etched in PMD)
 Contact pre-clean (remove particles, contaminants and native oxide)
 Metal deposition
 Sintering or annealing process
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FORMATION OF HEAVILY DOPED REGIONS
 Dopants selectively introduced through ion implantation or diffusion process
 Masking layer is used to restrict the introduction of dopants into the desired regions
 Heavy doping is needed, however the maximum doping concentration is limited by the solid
solubility of material.
 Clustering effect may reduce the electrically active dopants
ND > 1019
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FORMATION OF CONTACT OPENING
 Key step in the fabrication of contact structure
 The minimum size of contact holes usually determined by the minimum resolution capability
of patterning technology. Contact size normally the same as gate length for e.g 0.5um CMOS
technology, gate length = 0.5um, contact size = 0.5um (refer to the design rules).
 In older technology (>2.0um process), wet etching is used for contact etch. Wetting and by product
is introduced into the oxide etchant plus the application of ultrasonic agitation.
 Due to the isotrapic nature of wet etching, it is ineffective for the etching of smaller contact holes.
 Dry etching of contact etch is developed.
ND > 1019
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ND > 1019
ND > 1019
 Dry etch introduced a new set of problems;
 polymer contamination – by product of dry etching.
 damage of silicon surface (high energy radicals in plasma), this plasma also could damaged
gate oxide (plasma damaged, antenna structure is used to monitor this effect to oxide reliability)
 selectivity problem
 Several approaches used;
 additional step to remove polymer
 combined isotropic and anisotropic dry etch
 combination of dry and wet etch
 many others
ND > 1019
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SIDEWALL CONTOURING
 To give a shape that will result in good step coverage of metal.
 Several approaches used;
 reflow, high temperature furnace annealing after contact etch
 wet etching followed by dry etch process
 PR contouring followed by dry etch
 many others
Sloped opening
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REMOVAL OF NATIVE OXIDE
 Native oxide could result in high Rco
 2 – 5 Å oxide posed not problem since it can be consumed by metals during sintering
 Metal must be immediately deposited after native oxide removal
 Methods of removing native oxide
 H2O:HF (100:1) dip for 1 minute, followed by rinsing and drying
 Sputter etch contact in sputtering system prior to metalization
 in-situ dry-etch (no commercial product available) Native oxide growth rate on Si exposed to room air
Thickness (Å)
100
50
10
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100
1000 Time (min)
METAL DEPOSITION AND PATTERNING
 Major issue is metal step coverage in the contact holes
 Metal deposition technique is important;
 CVD is more capable to produce good step coverage (W plug, blanket or selective deposition)
 The drawback is process complexity and increase cost per process step
 Preferred deposition technique for high aspect ratio contact, > A.R of 3
 PVD at elevated temperature (300-350 C)
 Hot aluminum PVD process (400-500 C)
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SINTERING THE CONTACTS
 Performed to allow any interface layer that exists between the metal and silicon to be consumed
by a chemical reaction.
 to allow metal and silicon to come into intimate contact through inter-diffusion.
 Methods;
 400-500C for 30 minutes in the presence of H2 or forming gas (a mixture of H2 (10%) and N2 (90%)
 RTP, laser annealing and several others.
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ALUMINUM JUNCTION SPIKING
 Aluminum is chosen as metal interconnect because of;
 Al-Si ohmic contact could be fabricated with low Rco to n+ and p+
 low resistivity (2.7 Ohm-cm)
 excellent compatibility with SiO2 (good adhesion).
 the drawback is low melting point (660C) and low eutectic temperature of Al/Si mixtures (577 C)
 Grain boundaries of polycrystalline Aluminum provide fast diffusion path for Si at temperature > 400 C .
 As a result, large quantity of Si from Al-Si interface can diffuse into the Al film
 Simultaneously Al from film will move rapidly to fill the voids created by the departing Si.
 If the penetration of Al is deeper than the p-n junction depth below the contact, the junction will exhibit
large leakage current / electrically shorted.
 This effect is referred as junction spiking.
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Beginning of heat treatment
Si Si Si
During heat treatment
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METHOD TO REDUCE JUNCTION SPIKING
 Silicon is added to the Al film during deposition.
 sputter depositing the film from a single target containing both Al and Si.
 co-evaporation of Si and Al
 Silicon diffusion into Al will not occur if added Si concentration exceeds the Si solubility at process
temperature (normally 1 to 2 wt % Si is added).
However, this solution is only suitable for tchnology of 3um and above due to Si precipitation, thus increasing
the Rco.
 The introduction of Diffusion Barrier between Al and Si (typical solution to junction spiking in the
sub-micron CMOS process)
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DIFFUSION BARRIERS
 The role of this material is to prevent the inter- diffusion of Al and Si.
 A diffusion barrier used is a thin film inserted between an overlying metal and underlying semiconductor
material.
 Such diffusion barriers should have the following characteristics;
 diffusion of Al and Si through it should be low
 barrier materials should be stable in the presence of Al and Si
 barrier materials should adhere well to both Al and Si
 barrier materials should have low contact resistivity to Al and Si
 barrier materials should have good electrical conductivity
 3 types of barriers
 passive barriers (chemically inert with respect
to Al and Si.
 sacrificial barriers (react with Al and Si)
 stuffed barriers (its grain boundaries is
filled with other materials to block
inter diffusion of Al and Si.
Diffusion barrier
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DIFFUSION BARRIER MATERIALS
 Titanum – tungsten (Ti:W) – Stuffed Barrier
 Normally sputter-deposired from a single target.
 Initially used in Bipolar technology.
 Major draw-back for VLSI application is the film is quite brittle and of high stress.
 Polysilicon – Sacrificial Barrier
 Easily integrated into NMOS technology but not as compatible with CMOS
 Titanium – Sacrificial Barrier
 Good diffusion barrier to Si, has a relatively short barrier capability lifetime.
 Titanium Nitride – Passive Barrier
 The most compatible and successful diffusion barrier in CMOS process.
 impermeable barrier to Si
 high activation energy for the diffusion of other materials.
 chemically and thermodynamically very stable.
 the lowest electrical resistivity among transitory metals.
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THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS
TRANSISTOR PERFORMANCE
 Series resistance Rs is a combination of;
 Rs = Rco + Rsh + Rsp + Rac
ℓ
Contact length
METAL
PMD
GATE
Xj
Rac
Rco
Rsh
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Rsp
THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS
TRANSISTOR PERFORMANCE
 When larger design rules were used, Rs was a minor component of the total MOS resistance.
 As devices got smaller, Rs grew larger due to;
 shrinking contact size (Rco is dependence on contact size)
 shallower source / drain regions (Rsh is dependence on source / drain depth and width)
 under such conditions, Rs would degrade the device performance such as;
 Idsat, transconductance, Vt
 Rch = [Leff + VDS] / [0 Cox (VGS – VT – 0.5VDS]
 Generally accepted that Rs to be kept < 10% of Rch.
 A comprehensive analysis on the Rs components is needed to find the major contributor to the
Rs and ways to reduce it.
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SUMMARY OF THE ANALYSIS
 Rsh contribution is negligible
 The value of (Rac + Rsp) is likely to dominate the value of Rs for MOS devices with the channel
length of < 0.5um. Minimum value of (Rac + Rsp) are achieved by fabricating source/drain
junction with as steep a doping profile as possible.
 Rco can also important in degrading MOS device performance. Rco is essentially determined by;
 value of specific contact resistivity, ρc
 contact length, ℓ. It was shown that ℓ will need to be 1 to 4 times the channel length, L, to
produce with minimum value of Rco.
ℓ
Contact length
GATE
L
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The requirement on minimum ℓ meaning the new way of performing
contact structure is needed for deep sub-micron process technology.
WHY ???
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 It is not possible to increase the contact size, ℓ, because it will defeat the purpose of
device shrinkage.
 Enlarge active area (to accommodate larger ℓ) will also resulted in increased parasitic
junction capacitance, which further degrade the device performance
n+ diffusion
2λ
2λ x 2λ
W=4λ
λ
DRAIN
2λ
Z=2λ
5λ
L=2λ
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ALTERNATIVE CONTACT STRUCTURES
 self-aligned silicides (SALICIDE)
 buried-oxide MOS (BOMOS) contact
 elevated source / drain
 selective metal deposition
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Materials for Silicide Process
 Group – VIII metal silicides
 PtSi
(28-30 ohm-cm)
 CoSi2
(16-18 ohm-cm)
 NiSi2
(50
Ohm-cm)
 TiSi2
(13-20 ohm-cm)
 TiSi2 and CoSi2 are the most developed silicide process mainly because of;
 lowest resistivities among the group members
 stable at temperature ~ 850 C
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Silicide Process
Purpose : To reduce contact resistance, Rco between metal and silicon interface
PMD
GATE
1.
2.
Contact etch
Resist strip
n+
GATE
n+
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PMD
3. Titanium deposition by
sputtering technique
~ 400Å
PMD
GATE
4. TiN (barrier) deposition by
sputtering technique
~ 1000 Å
n+
PMD
GATE
n+
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TiSi2
5. TiSi2 (titanium silicide) formation by
RTP annealing, 700C @ 30s
PMD
GATE
n+
6. W Plug deposition ~ 6000 Å (by CVD)
and etch back.
TiSi2
7. AlSiCu deposition by sputtering
~ 3000 Å
PMD
GATE
n+
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TiSi2
8. TiN (ARC) deposition by sputtering
~ 1400 Å
PMD
GATE
TiSi2
n+
9. Metal-1 pattern and etch
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SALICIDE Process
GATE
1.
2.
After S/D implant
Resist strip
GATE
3. Titanium deposition by
sputtering technique
n+
n+
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TiSi2
GATE
4. TiSi2 (titanium silicide) formation by
RTP annealing, 700C @ 30s
n+
TiSi2
GATE
n+
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5. Unreacted metal is selectively etched
by etchant that does not attack the
silicide, SiO2 and Si substrate
GATE
6. PMD Deposition and reflow
n+
GATE
n+
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7. Contact pattern and etch
Then to be deposited with TiN (barrier),
W plug, AlSiCu and TiN (ARC).
Advantages of SALICIDE over conventional contact
 The value of Rsh becomes negligible, ρsh silicide = 1-2 Ohm/sq versus diffused junction = 40-120
ohm/sq
 Rs = Rco + Rsh + Rsp + Rac
 Contact area of silicide and the Si is much larger, thus, lower Rco for the same ρc
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