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EMT362: Microelectronic Fabrication
Hot Carrier Effect In Sub-Micron
MOSFET
Ramzan Mat Ayub
School of Microelectronic Engineering
School of Microelectronic Engineering
Lecture Objectives
• Able to describe the main carrier injection mechanisms such as CHE,
DAHC, F-N & Direct Tunneling.
• Able to describe the rootcause for the carrier injection and it’s signature
• Able to describe the structure formations for hot carrier effect supression
in MOSFET such as DDD and LDD.
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Gate Oxide Requirements
• Possible to grow thin oxide precisely and uniformly across the wafer
• Adequate reliability characteristics under operating conditions in terms
of strength (Breakdown Voltage), Reliability of operation over specified
time (τBD, QBD) and resistance to hot-carrier degradation.
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Carrier Injection in MOSFET
2 Type of Injection Mechanisms
1. Hot-carrier injection
The injection of carriers over the energy barrier
a) Channel Hot Electron Injection, CHE
b) Drain Avalanche Hot Carriers (DAHC)
2. Cold-carrier tunneling
The injection of carriers through the energy barrier
a) Fowler Nordheim (FN) Tunneling
b) Direct Tunneling
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No external bias, V=0
Ec
In ideal case, assume
qs
qm
Ei
qF
EFm
EFs
Ev
Metal
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Oxide
Work function – energy required to remove
an electron from fermi level to outside
of the material.
P-type s-conductor
m  s
V>>0
E
Hot carrier injection
Inversion
Cold carrier tunneling
----
Ec
Ei
EFs
qV
EFm
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Ev
A. Channel Hot Electron Injection (CHE)
electron affinity
• CHE occurs in when MOSFET is biased in strong
inversion.
E
----
3.1 eV
• Electric field accelerate the electrons in the
channel, until some carriers acquire enough
energy and become hot.
• These hot carriers can surmount EFm
the energy barrier and jump into the oxide.
Ei
EFs
qV
• Since the energy barrier for electron injection is smaller,
the probability of hot-electron injection is far greater than
for hot-hole injection.
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Ec
Ev
4.9 eV
hole affinity
• Hence, the problem of hot-carrier injection is much worse in n-channel
MOSFET.
• Once the electrons are injected into the oxide, they can be transported
to the gate electrode (as gate current), or returned back to the substrate
as substrate current.
• The injection is expected to take place at where the lateral electric field
field is at the maximum.
• The study shows maximum electric field, Eymax occurs near the drain.
n+
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e-
n+
ID
• The CHE gate current increases
as VGS is increases.
VD = 14V
• The gate current peaks
at the point where VGS = VDS
VD = 12V
VD = 10V
4
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8
12
16
20
24
VG
B. Drain Avalanche Hot Carriers Injection (DAHC)
• Energetic electrons accelerated by electric field can produce additional
carriers by impact ionization.
• Electron-hole pair created as a result of impact ionization
• The created electrons are either collected by drain or injected into the
oxide, while holes give rise to substrate current.
• Excessive substrate current can lead to unwanted behaviour such as
latch-up.
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ID
CHE
DAHC
electron
hole
0
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2
4
6
8
10
VG
C. Fowler Nordheim Tunneling
• This type of injection is due to the quantum-mechanical nature of electron.
• The wave nature of electron (hole) allows it to cross the energy barrier
even if electron (hole) does not posses sufficient kinetic energy (3.1eV
and 4.9 eV respectively)
• This probability increases with larger electric field and thinner barriers.
• Electrons are injected by tunneling into oxide through triangular energy
barrier.
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E
• Once injected, electrons are accelerated
FN tunneling
by the oxide field towards
the gate, causing a gate current.
• By solving the Schrodinger’s wave equation
for a triangular barrier, tunneling current
could be estimated.
J  AF ox exp(  B / ox)
2
Where AF = 1.25e-6 A/V2, B~240 MV/cm
J is current density in A/cm2 and ox is oxide field.
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Inversion
----
Ec
D. Direct Tunneling
• For a very thin oxide (less than 6 nm), tunneling current is observed to
exhibit weak dependence on electric field.
• This is thought to be due to a direct tunneling through the forbidden gap
of SiO2 to the gate electrode.
E
Inversion
----
Direct tunneling
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Ec
VGS
VDS
n+
E = V/x
n+
The most widely used approach to improve chip performance (speed) is by scaling down the device.
Weff
KP
________
[ 2 (VGS – VT) VDS – V2DS ] ( 1 + LAMBDA x VDS)
IDS =
Leff 2
 As the device dimensions are reduced, and supply voltage remains constant, the lateral
electric field in the channel increase.
 This causes the carriers to be accelerated to an extent that they can cause a number of harmful
phenomena
 This phenomena is called the hot carrier effect.
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VGS
VDS
2
n+
e
e
e
1
n+
3
1 – high velocity electrons will create electron-hole pair by impact ionization process
2 – electrons will be injected into the gate oxide
3 – hole will be escaped as substrate current (long-term device degradation, used to predict
m
device lifetime)
  B( Isub / Z )
Time-dependent (reliability) degradation to MOS characteristics (2);
 threshold voltage shift
 lower gate oxide τBD and QBD
 linear region transconductance
 subthreshold slope (switching speed – speed of the channel to turn on / off)
 saturation current
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Techniques for Reducing Hot Carrier Degradation
1.
2.
3.
To decrease channel lateral electric field by lowering the power supply voltage, for e.g.
5V to 3.3V and so on.
To improve the characteristics of gate oxide (more resistance to electron injection)
To reduce the channel lateral electric field at drain-end of the channel (εymax).
VGS
1
VDS
2
n+
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3
Ey
n+
Maximum Channel Lateral Electric Field
• Maximum lateral electric field occurs near the drain.
• The study shows no significant hot-carrier effect occurs at values of
εymax less than 4e4 V/cm (Electric field value at which electrons are
velocity saturated)
Eymax = (VDS – VDSsat) / ℓ
Effective length of VSR
Pinch-off voltage
Where
ℓ = 0.22 tox1/3 xj1/3
= 1.7 x 10-2 tox1/8 xj1/3 L1/5
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for tox > 15 nm
for tox <15nm and L < 0.5m
REDUCING HOT-CARRIER DEGRADATION BY MODIFYING MOSFET STRUCTURE
VGS
VDS
n+
nEy
n+
 Increasing L will defeat the purpose of device scaling.
 Increasing tox and xj will worsen the short channel effect susceptibility.
 General approach is to create a lightly doped region at the drain end of the channel i.e. drain with
lightly-doped extension.
 Eymax is reduced because the voltage drop becomes shared by the drain and the channel
 This technique generally known as graded-junction drain (compared to abrupt junction).
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TECHNIQUES TO PRODUCE GRADED-JUNCTION DRAIN
1.
Using Phosphorus in place of Arsenic as a dopant for source / drain regions.
2.
Use both P and As. P diffuse faster than As to form graded junction (DDD – double-diffused drain)
3.
Use “oxide spacer” to create LDD (lightly doped drain) structure.
4.
Advanced LDD structures
Design
Rules
3.5 um
2.5 um
1.75 um
1.25 um
0.9 um
Effective
Channel
Length
2 um
1.5 um
1.3 um
1.0 um
0.75 um
350 A
250 A
200 A
150 A
N-LDD
N & P LDD
Gate
600 A
Oxide Thc
Convention Convention DDD
Drain
al
Structure al
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DOUBLE-DIFFUSED DRAIN (DDD) STRUCTURE
1.
2.
3.
Both dopants are co-implanted into the same region using 2 separate implants.
P ~ 1 X 1014 cm-2, As ~ 5 x 1015 cm-2.
High temperature anneal
Phosphorus implant
PR
POLY
PR
P-well
Annealing
Arsenic implant
PR
POLY
PR
POLY
n+
n+
nP-well
P-well
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ADVANTAGES OF DDD
1.
2.
Easy implementation (can be introduced without additional masking step).
Consistent device characteristics (both implantations aligned to the same gate edge)
DIS-ADVANTAGES OF DDD
1.
2.
3.
4.
5.
No freedom to optimize the length of n- region.
Need a long thermal drive-in, caused a deep vertical P junction.
Long drive-in also causes re-distribution of dopants in the channel (Vt adjust)
More prone to punchthrough due to deep phosphorus vertical junction.
Not suitable for DR of 1.25um and below.
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LIGHTLY-DIFFUSED DRAIN (LDD) STRUCTURE
1.
2.
3.
The most widely used structure for hot carrier suppression for DR of < 1.25 um.
Drain is formed by two implants. The 1st implant is self-aligned to gate electrode to form n- region.
The 2nd implant is done after the formation of “oxide spacer”, to form n+ region.
Phosphorus implant
PR
POLY
PR
P-well
Arsenic implant
Spacer formation
POLY
P-well
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PR
POLY
P-well
PR
LIGHTLY-DIFFUSED DRAIN (LDD) PROCESS SEQUENCE
 Well formation
 LOCOS
 Poly deposition
P-well
POLY
 Poly etch
P-well
PR
POLY
P-well
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PR
Poly re-ox
n-LDD implant, self-aligned to gate.
 Spacer oxide deposition (TEOS oxide)
POLY
P-well
 Spacer oxide etch
POLY
P-well
Arsenic implant
PR
POLY
P-well
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PR
 Arsenic implant self-aligned to spacer,
n+ for source/drain regions
DISPOSABLE SPACER LIGHTLY-DIFFUSED DRAIN (LDD)
P-well
POLY
 Well formation
 LOCOS
 Poly deposition
 Poly etch
P-well
POLY
P-well
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Poly re-ox
Spacer oxide deposition
 Spacer oxide etch
POLY
P-well
Arsenic implant
PR
POLY
PR
 Arsenic implant self-aligned to spacer,
n+ for source/drain regions
P-well
POLY
P-well
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 Spacer strip (BOE)
PR
POLY
P-well
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PR
 n-LDD implant, self-aligned to gate.
BURIED LIGHTLY-DIFFUSED DRAIN (B-LDD) – 0.5um to 0.25um CMOS
POLY
Conventional LDD
As
P
P-well
POLY
Buried- LDD, tilted deep implant
P-well
As
POLY
Graded Buried- LDD, tilted deep
implant
P-well
P
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As
HALO-SOURCE- GATE OVERLAPPED DRAIN (commonly used in <0.25um CMOS
and below – combined with SALICIDE)
 TO SUPPRESS HOT CARRIER (on-state) AND PUNCHTHROUGH (off-state)
 n- region formed only on the drain side by LAT implant for hot-carrier effect suppression
 p- region formed only on the source side by LAT implant for punchthrough suppression
POLY
n+
pP-well
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n-
n+