Transcript Advancing RIT to Submicron Technology: Design and

Development of a Deep-Submicron
CMOS Process for Fabrication of High
Performance 0.25 m Transistors
Michael Aquilino
Microelectronic Engineering Department
Rochester Institute of Technology
April 21, 2005
Motivation



Enable the Microelectronic Engineering
department to continue the
semiconductor industry trend of
fabricating high performance transistors
that have faster switching speeds,
increased density and functionality, and
ultimately a decrease in cost per function.
Push the limits of the SMFL in all areas
from design to fabrication to test
Create a baseline process that can be
used to integrate strained silicon, metal
gates, high-k gate dielectrics, and
replacement gate technologies at RIT
Rochester Institute of Technology
Microelectronic Engineering
2
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
3
RIT/Industry Scaling Trends
Table 1: RIT/Industry Scaling Trends [3]
Gate Length Frequency Transistors Supply Voltage
Date
Processor Family
(μm)
(V)
November 1971
4004
10
108 KHz
2,300
15
April 1974
8080
6
2 MHz
6,500
12
June 1978
8086
3
10 MHz
29,000
5
February 1982
Intel 80286
1.5
12 MHz
134,000
5
March 1995
Intel Pentium
0.6
120 MHz
3,300,000
3.5
**May 2004
RIT Submicron NMOS
0.5
3.5
August 1999
Intel Pentium 2 & 3
0.25
600 MHz
9,500,000
2.0
**September 2005 RIT Deep-Submicron CMOS
0.25
2.0
September 2001
Intel Pentium 3 & 4
0.18
2.0 GHz
45,000,000
1.7
February 2004
Intel Pentium 4
0.13
3.4 GHz
55,000,000
1.5
June 2004
Intel Pentium 4
0.09
3.6 GHz 125,000,000
1.4
o
Over last 30 years, transistors have gotten smaller and faster
o 110x reduction in gate length
o 36,000x increase in switching speed
o
Integrated circuits have become much more complex
o 54,000x increase in number of transistors on an IC
Rochester Institute of Technology
Microelectronic Engineering
4
RIT/Industry Scaling Trends
Table 1: RIT/Industry Scaling Trends [3]
Gate Length Frequency Transistors Supply Voltage
Date
Processor Family
(μm)
(V)
November 1971
4004
10
108 KHz
2,300
15
April 1974
8080
6
2 MHz
6,500
12
June 1978
8086
3
10 MHz
29,000
5
February 1982
Intel 80286
1.5
12 MHz
134,000
5
March 1995
Intel Pentium
0.6
120 MHz
3,300,000
3.5
**May 2004
RIT Submicron NMOS
0.5
3.5
August 1999
Intel Pentium 2 & 3
0.25
600 MHz
9,500,000
2.0
**September 2005 RIT Deep-Submicron CMOS
0.25
2.0
September 2001
Intel Pentium 3 & 4
0.18
2.0 GHz
45,000,000
1.7
February 2004
Intel Pentium 4
0.13
3.4 GHz
55,000,000
1.5
June 2004
Intel Pentium 4
0.09
3.6 GHz 125,000,000
1.4
o
In May of 2004 an NMOS transistor with LPOLY = 0.5 µm was developed
o
This is RIT’s smallest transistor with LEFFECTIVE = 0.4 µm
o
This is the same technology as the Intel Pentium from 9 years earlier
Rochester Institute of Technology
Microelectronic Engineering
5
RIT/Industry Scaling Trends
Table 1: RIT/Industry Scaling Trends [3]
Gate Length Frequency Transistors Supply Voltage
Date
Processor Family
(μm)
(V)
November 1971
4004
10
108 KHz
2,300
15
April 1974
8080
6
2 MHz
6,500
12
June 1978
8086
3
10 MHz
29,000
5
February 1982
Intel 80286
1.5
12 MHz
134,000
5
March 1995
Intel Pentium
0.6
120 MHz
3,300,000
3.5
**May 2004
RIT Submicron NMOS
0.5
3.5
August 1999
Intel Pentium 2 & 3
0.25
600 MHz
9,500,000
2.0
**September 2005 RIT Deep-Submicron CMOS
0.25
2.0
September 2001
Intel Pentium 3 & 4
0.18
2.0 GHz
45,000,000
1.7
February 2004
Intel Pentium 4
0.13
3.4 GHz
55,000,000
1.5
June 2004
Intel Pentium 4
0.09
3.6 GHz 125,000,000
1.4
o
By September of 2005, this process will yield CMOS transistors
with LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm
o
This technology was used in high volume manufacturing of the Intel
Pentium III at 600 MHz only 6 years ago
o
The gap between industry and RIT is rapidly shrinking
Rochester Institute of Technology
Microelectronic Engineering
6
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
7
Gate Control Fundamentals
o
NMOS Transistor
o
4 Terminal Device
o Gate
o Source
o Drain
o Body
Figure 1: Schematic of NMOS Transistor [4]
To turn transistor on:
o Apply positive charge to Gate, QG
o A depletion region in the p-type body is created as positively
charged holes are repelled by gate, exposing negatively charged
acceptor ions, QB
o As the gate charge is further increased, electrons from the source
diffuse into the channel and become inversion charge, QI
o QG = QB + QI
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Microelectronic Engineering
8
Gate Control Fundamentals
o
The source and body
terminals are grounded
o
A positive voltage is
applied to the drain, VDS
o
Inversion charge moves
from source to drain and
is the current in the device
o
Figure 1: Schematic of NMOS Transistor [4]
Equation 1 shows the classical derivation for drain current in a
transistor by integrating the inversion charge along the channel
W
ID 
L
Rochester Institute of Technology
Microelectronic Engineering
VD

VS
nQn(V )dV
(Eq. 1)
9
Gate Control Fundamentals
o
A depletion region from
the drain is created by the
reverse biased body-drain
p-n+ diode
o
The positively charged
donor ions in drain support
some of the negative
inversion charge
Figure 1: Schematic of NMOS Transistor [4]
o
This is known as “Charge Sharing” as the gate does not have full
control over the inversion channel
o
For large gate lengths, the contribution of the drain in controlling
the inversion layer is small compared to the gate contribution
o
As transistors are scaled smaller in gate length, the drain has a
larger percentage contribution in supporting inversion charge in
the channel
Rochester Institute of Technology
Microelectronic Engineering
10
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
11
Short Channel Effects
o
“Gate Control” is the most important concept in scaling of transistors
o
The consequence of the drain taking control away from the gate
is short channel effects such as:
o VT Roll-off
o Drain Induced Barrier Lowering (DIBL)
o Punch-through
Threshold Voltage
(volts)
Vt Rolloff vs. Leff
o
Threshold voltage decreases
as gate length decreases
o
For small enough gate lengths
the devices will be on at 0 V
1
0.8
0.6
0.4
0.2
0
0.4
0.5
0.6
0.7
0.8
0.9
1
Leff (um )
Figure 2 : VT Roll-off Effect [1]
Rochester Institute of Technology
Microelectronic Engineering
12
Short Channel Effects
o
“Gate Control” is the most important concept in scaling of transistors
o
The consequence of the drain taking control away from the gate
is short channel effects such as:
o VT Roll-off
o Drain Induced Barrier Lowering (DIBL)
o Punch-through
o
Increased off-state leakage with
increase in drain voltage
o
If gate were in full control, these
curves would be one on top of the
other
Figure 3: Drain Induced Barrier Lowering (DIBL) [1]
Rochester Institute of Technology
Microelectronic Engineering
13
Short Channel Effects
o
“Gate Control” is the most important concept in scaling of transistors
o
The consequence of the drain taking control away from the gate
is short channel effects such as:
o VT Roll-off
o Drain Induced Barrier Lowering (DIBL)
o Punch-through
o
At high drain bias, the drain
takes control of current
through the device
o
Excessive heating can occur
and cause device failure
Figure 4: Lateral source/drain Punch-through [4]
Rochester Institute of Technology
Microelectronic Engineering
14
Short Channel Effects
o
“Gate Control” is the most important concept in scaling of transistors
o
The consequence of the drain taking control away from the gate
is short channel effects (SCE) such as:
o VT Roll-off
o Drain Induced Barrier Lowering (DIBL)
o Punch-through
o
Transistors with short channel effects are undesirable
o
These SCE must be minimized to yield long-channel transistors
Rochester Institute of Technology
Microelectronic Engineering
15
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
16
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Figure 5: Physical Scaling Guidelines [7]
Rochester Institute of Technology
Microelectronic Engineering
17
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
o
o
o
o
o
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Decrease gate oxide thickness
Gate is closer to the channel
More control in switching device off
Cox  since Cox = A/tox or Cox =Q/V
ID and gm  since  Cox
Figure 5: Physical Scaling Guidelines [7]
Rochester Institute of Technology
Microelectronic Engineering
18
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Decrease junction depth of source/drain
o Depletion region from gate dominates
depletion region from the drain
o Trade-off is sheet resistance  and ID 
o ND must  which will cause RS 
o
Figure 5: Physical Scaling Guidelines [7]
Rochester Institute of Technology
Microelectronic Engineering
19
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Use sidewall spacer to create deeper
source/drain junction called the contact
o Typically ~2x as deep as shallow LDD
o Doped heavily to reduce RS
o
Figure 5: Physical Scaling Guidelines [7]
Rochester Institute of Technology
Microelectronic Engineering
20
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Increase doping of channel to decrease
the depletion region from the source/drain
o Use a retrograde profile where doping is
low at the surface and higher sub-surface
o Mobility of carriers 
o ID and gm  since both are  mobility
o
Rochester Institute of Technology
Microelectronic Engineering
Figure 5: Physical Scaling Guidelines [7]
21
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
o
As TOX , gate leakage current 
o
VDD must  to reduce this leakage
o
VT must  so (VGS-VT) , this is “Gate Overdrive” and is  ID
o
Want ION  since gate delay  ION-1
Rochester Institute of Technology
Microelectronic Engineering
RC

ION
22
Deep-Submicron Scaling
The goal in deep-submicron scaling is to maximize the gate
control for switching the device on and off by scaling physical
and electrical parameters
o
Table 2: 0.25 µm Scaling Parameters from NTRS Roadmap [6]
ION
600 A/μm
IOFF
1 nA/μm
Log(ION / IOFF) 5.75 decades
SS
85 mV/decade
DIBL
< 100 mV/V
VDD
1.8 – 2.5 V
| VT |
0.5 V
o
o
o
o
o
Tox
40 - 50 Å
XJ (shallow LDD)
50 – 100 nm
ND (LDD)
2 - 5 x1018 cm-3
RS (LDD)
400 – 850 sq
XJ (contact)
135 – 265 nm
ND (contact)
1x1020 cm-3
XJ (SSRW channel)
50 – 100 nm
Want IOFF to be low to reduce standby power
The industry standard metric is 1 nA/µm of off-current
This results in 5.75 decades between ION and IOFF
There is 500 mV swing between 0 V and VT
SS of 85 mV/decade is needed to turn the device off
SS 
KT
CD 

 ln10  1 
q
 COX 
Rochester Institute of Technology
Microelectronic Engineering
Theoretical limit ~ 60 mV/decade
@ 300K
23
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
24
0.25 µm Device Technology
o
Unit Processes will be developed to yield cross-section shown in Figure 6
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P+ S/D
TiSi2
P-SSRW
P-Well
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 6: CMOS Cross Section showing NMOS (left) and PMOS (right) Transistors
• Shallow Trench Isolation
 Dual Doped Poly Gates
 50 Å gate oxide w/ N2O
 Low Doped Source/Drain Extensions
 Titanium Silicide
Rochester Institute of Technology
Microelectronic Engineering
• Super Steep Retrograde Twin Well
 Nitride Sidewall Spacers
 Rapid Thermal Dopant Activation
 2 Level Aluminum Metallization
 Back End CMP
25
Unit Process Development

Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
P-Well
Gate Formation
N-Substrate
 Lithography
Figure 7:
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Aluminum
Nitride Spacers
P+ Poly
N+ Poly

P+ Well
Contact







LDD
P-SSRW
Rochester Institute of Technology
Microelectronic Engineering
STI
N+ S/D
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
Shallow Trench Isolation
26
Shallow Trench Isolation
o
Replacement of LOCOS as preferred isolation technology
o
LOCOS suffers from “Bird’s Beak” effect
o Field oxide encroaches into active region, reducing W
o Reduction in Width leads to reduction in drive current
o To recover this loss, transistors must be made wider
which takes up more real estate
o Small geometries are not possible since Bird’s Beak
oxide encroaches from both sides of active area
o
With STI, WACTUAL ≈ WDRAWN
o Increased packing density
o Higher drive current for devices with same WDRAWN
o
Decreased topography early in the process
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27
Shallow Trench Isolation
o
o
o
Grow Pad Oxide
Deposit Nitride by LPCVD
Pattern and Etch Silicon Trench
Figure 8: STI Process after trench etch
Grow liner oxide to repair silicon
and round off sharp corners
o Fill with PECVD TEOS Oxide
o
Figure 9: STI Process after trench fill
o
o
o
CMP trench oxide
Use Nitride as etch stop
Remove Nitride in H3PO4 acid
Figure 10: STI Process after CMP
Rochester Institute of Technology
Microelectronic Engineering
28
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
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Microelectronic Engineering
29
Channel Engineering
Aluminum
Aluminum
Nitride Spacers
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
Nitride Spacers
P+ Poly
N+ Poly
P+ S/D
TiSi2
N+ Well
Contact
LDD
P+ Well
Contact
N-SSRW
P-Well
P+ Poly
N+ Poly
STI
N+ S/D
LDD
P-SSRW
P-Well
N-Well
N-Substrate
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 11: Uniformly Doped Twin Wells
Figure 12: Super Steep Retrograde Wells
Uniformly Doped Twin Wells
Super Steep Retrograde Wells
NMOS built in p-well
o PMOS built in n-well
o Set Field VT to stop parasitic
conduction channels from
forming between adjacent
devices
o
o
Rochester Institute of Technology
Microelectronic Engineering
2nd step in well formation process
o Lower doping at surface which
transitions to higher doping
sub-surface
o Control short channel effects
o Set active VT
30
Uniformly Doped Twin Well
o
In industry, wells are implanted through
the trench oxide with energies of 1 MeV
to place the peak 1 µm below the surface
oThe
limit of the Varian 350D Ion Implanter
is 190 KeV which is not high enough to
implant through 3000 Å of trench oxide
o
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P-Well
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 11: Uniformly Doped Twin Wells
Also, there will be non-uniformities in silicon trench depth and
TEOS oxide fill.
For packing density purposes, multiple active regions are built in the
same well with 1 common contact
o
It is therefore required for the well doping to be continuous under
the trench oxide regions
o
o
For this process, the wells will be implanted before the trench oxide
fill inRochester
theInstitute
STIofprocess
to ensure the wells are continuous in the field
Technology
Microelectronic Engineering
31
Uniformly Doped Twin Well
Table 3: Field Region VT
Field Region
FOX
3000 Å
NSUB
1x1017 cm-3
VTN
13 V
VTP
-15 V
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-Well
N-Well
N-Substrate
Figure 11: Uniformly Doped Twin Wells
o
A drive-in thermal step will create uniform wells with:
o ND = 1x1017 cm-3
o XJ-WELL = 1 µm
o
With a 2.0 V supply, the field-VT is sufficiently large
o
The junction depth of the wells must be large enough to prevent
vertical punch-through between the reverse-biased drain and
complimentary doped starting wafer
o
A junction depth of 1 µm will provide more than enough tolerance
Rochester Institute of Technology
Microelectronic Engineering
32
Super Steep Retrograde Well
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P-Well
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 12: Super Steep Retrograde Wells
o
Increased carrier mobility due to lower channel doping at surface
o
Increased drive current due to increased mobility
o
Suppression of short channel effects (SCE) such as VT roll-off, punchthrough, and drain induced barrier lowering (DIBL) due to the higher
peek doping sub-surface
o
Latch-up is suppressed because the base regions of parasitic BJTs are
doped higher, therefore reducing their gain.
Rochester Institute of Technology
33
Microelectronic Engineering
Super Steep Retrograde Well
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P-Well
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 12: Super Steep Retrograde Wells
o
Increased carrier mobility due to lower channel doping at surface
o
Increased drive current due to increased mobility
o
Suppression of short channel effects (SCE) such as VT roll-off, punchthrough, and drain induced barrier lowering (DIBL) due to the higher
peek doping sub-surface
o
Latch-up is suppressed because the base regions of parasitic BJTs are
doped higher, therefore reducing their gain.
Rochester Institute of Technology
34
Microelectronic Engineering
Super Steep Retrograde Well
Lower surface
doping concentration
Peak channel concentration
Uniform well for Field VT
Figure 13: Super Steep Retrograde Profile [10]
o
o
o
Implanted after uniformly doped wells go through drive-in
In Industry, heavy ions that are slow diffusers are used:
o Indium (In) is used for p-well of NMOS
o Antimony (Sb) or Arsenic (As) are used for n-well of PMOS
At RIT, Boron and Phosphorous are available
o Boron (B) will be used for p-well of NMOS
o Phosphorous (P) will be used for n-well of PMOS
o Are more susceptible to transient enhanced diffusion (TED)
o Won’t produce profiles as steep as In or Sb but by keeping
thermal budget low, can still produce retrograde profiles
Rochester Institute of Technology
Microelectronic Engineering
35
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
36
50 Å Gate SiO2 with N2O Incorporation
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-SSRW
P-Well
N-Well
N-Substrate
Figure 14: Ultra Thin Gate Oxide
o
NTRS Roadmap suggests 40 – 50 Å, target for this process is 50 Å
o
ox = 4 MV/cm, this is at limit of Fowler-Nordheim tunneling
o
Nitrogen is incorporated into oxide to block diffusion of boron from
p+ poly gate into channel of PMOS transistor
o
Surface Charge Analysis can be done to determine density of interface
trap states.
Rochester Institute of Technology
Microelectronic Engineering
37
Unit Process Development



Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
N-Substrate
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Aluminum
P+ Well
Contact
Nitride Spacers
STI
N+ S/D
LDD





Rochester Institute of Technology
Microelectronic Engineering
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-SSRW

P+ Poly
N+ Poly
P-Well
N-Well
Figure 15: Poly Gate Formation
38
Gate Formation - Lithography
Figure 16: ASML DUV Stepper
o
o
Figure 17: Canon i-line Stepper
o Canon FPA-2000i1 stepper
ASML PAS 5500/90 stepper
o 365 nm i-line source
o 248 nm KrF excimer laser
o Capable of 0.5 µm lines/spaces
o Capable of 0.25 µm lines/spaces
Tool is currently down, laser
Rochester Institute of Technology
Microelectronic Engineering
o
Standard resist coat/develop track
o
Capable of 0.05 µm overlay error
39
Gate Formation – Resist Trimming
Figure 18: Resist Trimming Process
o
Resist trimming can be used to make 0.5 µm line a 0.25 µm line for gate
o
Isotropically etch 1250 Å of resist of sides and top of 0.5 µm line
o Resist thickness reduced from 10,000 Å to 8750 Å
o This is still sufficiently thick to protect poly during gate plasma etch
o
Line width reduced to 0.25 µm target in photoresist
o
This technique will be explored if over-exposing/developing is not successful
Rochester Institute of Technology
Microelectronic Engineering
40
Gate Formation – RIE Poly
o
Polysilicon thickness is reduced for smaller gate lengths
o 2500 Å target will provide 1:1 aspect ratio for plasma etch
o Will block up to 50 keV Phosphorous and 30 keV Boron
o
Want high selectivity of poly to oxide since oxide is very thin
o
Reactive Ion Etcher will be used since it etches anisotropically
o Etch rate is higher in the vertical direction compared to horizontal
o
If etch was isotropic, enough under-cut would occur due to lateral
etching that 0.25 µm would be etched away and remove the
photoresist masking layer
Before Etch
Rochester Institute of Technology
Microelectronic Engineering
After Etch
Figure 19: Under-Cut of Gate Mask
41
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
42
Poly Re-Oxidation
o
After plasma etch of gate there is damage to edges of gate oxide
o
A 250 Å oxide will be thermally grown to:
o Repair damage to gate oxide from
plasma etch of the poly gate
o
Create a thicker screening oxide for
source/drain extension implant
o
Make a thicker etch stop for sidewall
spacer etch process
o
Form an off-set region for lateral diffusion of shallow s/d extension
Figure 20: Poly Re-Oxidation
o
Want to reduce gate overlap of s/d to reduce Miller Capacitance
o This capacitance will reduce the cut-off frequency of the device
o
Need 15 – 20 nm overlap or drive current will degrade [11]
Rochester Institute of Technology
Microelectronic Engineering
43
Poly Re-Oxidation
LPOLY = 250 nm
XJ = 75 nm
52.5 nm
52.5 nm
LEFFECTIVE = 180 nm
Figure 21: Gate Overlap and LEFFECTIVE Calculation
o
Gate Overlap = 52.5 nm – 25 nm = 27.5 nm
o
Process is designed for LPOLY = 0.25 µm and LEFFECTIVE = 0.18 µm
Rochester Institute of Technology
Microelectronic Engineering
≥ 15 – 20 nm requirement
44
Low Doped Source/Drain Extensions
Aluminum
o
Shallow junctions implanted after
poly re-ox step
o
A portion of VDS is dropped across
the LDD so a lower effective voltage
is across the channel (Eq. 2)
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-Well
N-Well
N-Substrate
o
Figure 22: Low Doped Source/Drain Extensions
The advantage of this is reduced
hot carrier effects since carriers see lower horizontal electric field
Figure 23:
Equivalent Circuit
with Parasitic Resistance
Vchannel = VDS – 2*IDS(Rterminal + Rs/d + RLDD)
oThe
(Eq. 2)
trade-off is there will be a reduction in drive current & switching speed
Rochester Institute of Technology
Microelectronic Engineering
45
Low Doped Source/Drain Extensions
Table 4: NTRS Guidelines for LDD Scaling [6]
XJ(LDD)
RS (LDD)
ND(LDD)
NTRS Guidelines
0.4*Lpoly +/- 25%
Range
75 nm – 125 nm
400 – 850 sq
5.2x1018 – 2.5 x1018 cm-3
Target
75 nm
400 sq
5.2x1018 cm-3
o
Low end of range is chosen for XJ and RS so if more diffusion
occurs then is anticipated, the devices will still operate properly
o
The implant energy must be selected to place the peak of the
implant at the Silicon surface. With a 300 Å screening oxide layer:
o B11 of 10 keV
o P31 of 25 keV
o
The Varian 350D is capable of implant energies as low as 10 keV
o
In industry, Silicon (Si) or Germanium (Ge) are implanted before
the shallow S/D implants to reduce channeling of dopant ions
Rochester Institute of Technology
Microelectronic Engineering
46
Silicon Nitride Sidewall Spacers
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-SSRW
P-Well
N-Well
N-Substrate
Figure 24: Nitride Sidewall Spacers
o
Figure 25: SEM Micrograph of Nitride Spacer
Sidewall spacers are formed after the LDD implants to create an
offset region where a deeper source/drain contact region can be
implanted.
Re-oxidize Poly Gate
Ion Implant LDD
Deposit LPCVD Nitride
RIE Nitrde to form Spacers
Figure 26: Sidewall Spacer Process
Rochester Institute of Technology
Microelectronic Engineering
47
Silicon Nitride Sidewall Spacers
o
o
In a perfectly anisotropic etch the Lspacer = tpoly = 0.25 µm
Parasitic LDD resistance is controlled by length of sidewall spacer
RSAT  W 
VDD  tox
= 4108 µm
0.47  vsat  OX  VDD  VT 
RLDD  W  RSLDD  LTOTAL
(Eq. 3)
(Eq. 4)
VDD = 2.0 V
|VT| = 0.5 V
Tox = 50 Å
Table 5: Sidewall Spacer Length Effect on Drive Current [9]
RSLDD
Lspacer
LTOTAL  Lspacer  2
(/sq)
(m)
(m)
400
400
400
400
0.1
0.2
0.25
0.3
0.2
0.4
0.5
0.6
( xm)
R LDD  W
RSAT  W
80
160
200
240
1.9%
3.9%
4.9%
5.8%
RLDD  W
o
NTRS Guidelines require < 10% reduction in drive current due
to parasitic source/drain extension resistance
o
Source/Drain contact resistance must also be taken into account
Rochester Institute of Technology
Microelectronic Engineering
48
Source/Drain Contact
o
Source/Drain contacts implanted after sidewall spacer formation
and are self-aligned to the gate
Ion Implant Deep S/D
Contacts
N+/P+ Poly Gates
Implanted at same time
Figure 27: Source/Drain Contact and Gate Doping
o
Contact is doped higher and junction depth deeper to
decrease parasitic source/drain resistance
o
Silicide thickness must account for < ½ contact junction depth
or increased leakage current will result
Rochester Institute of Technology
Microelectronic Engineering
49
Source/Drain Contact
Table 6: NTRS Guidelines for Source/Drain Contact Scaling [6]
XJ(Contact)
ND(Contact)
RS(Contact)
NTRS Guidelines
0.8*LPOLY +/- 33%
Range
134 nm – 266 nm
Target
150 nm
1x1020 cm-3
50 – 75 /sq
o
Midpoint of XJ range chosen so XJ-CONTACT ~ 2*XJ-LDD
o
The implant energy must be ~ 2x higher then shallow LDD implants:
o B11 of 20 - 30 keV
o P31 of 40 - 50 keV
o
The sheet resistance of this region must be decreased to decrease
the reduction in drive current
o
The polysilicon gates are doped n+ for NMOS and p+ for PMOS at
the same time the contacts are doped.
Rochester Institute of Technology
Microelectronic Engineering
50
Dual Doped Poly Gates
o
Dual doped poly is used to create surface channel PMOS transistors by
engineering a better matched Metal-Semiconductor work function, MS
4sqNaB
V  VFB  2 
COX '
T
B
KT  Na 
B 
ln  
q  ni 
Qox
VFB  MS 
Cox
o
(Eq. 5)
(Eq. 6)
(Eq. 7)
Retrograde profile will be designed to set appropriate Na for the VT
equation in Eq. 5
Rochester Institute of Technology
Microelectronic Engineering
51
Dual Doped Poly Gates
o
Gate depletes body to a depth of WDMAX
o
Na transitions from 1x1017 cm-3 at surface
to 1x1018 cm-3 at the peek
o
The peak of each profile must be set such
that the effective Na the gate depletes
is what is required for |VT| = 0.5 V
Figure 28: Super Steep Retrograde Profile
With WDMAX [10]
o
Na(effective) for NMOS =6.75x1017 cm-3
o
Na(effective) for PMOS = 6x1017 cm-3
o
Lower surface concentration, higher sub-surface channel doping
and proper VT are all benefits of using a super steep retrograde well
Rochester Institute of Technology
Microelectronic Engineering
52
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
53
Rapid Thermal Dopant Activation
o
Need to repair damage to Si
lattice caused by ion implant
o
Electrically activate dopant atoms
o
Transient enhanced diffusion will
cause dopants to diffuse at
accelerated rate and cause deeper
then desired junction depths
o
Rapid Thermal Processing is used to
rapidly heat the wafer for a short
amount of time
o
Thermal budget for 0.25 µm device
is only 2-3 seconds @ 1000°C
Rochester Institute of Technology
Microelectronic Engineering
Figure 29: Thermal Budget for p+ Junctions
54
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
55
Titanium Silicide Formation (TiSi2)
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
P-SSRW
P-Well
N-Well
N-Substrate
Figure 30: Titanium Silicide Formation
o
Want to reduce sheet resistance of source/drain contact regions
from 50 – 75 /sq to 4 /sq
o
Want high drive current for fast switching speeds
o
Titanium Silicide was widely used at the 0.25 µm node and will
be used in this process
Rochester Institute of Technology
Microelectronic Engineering
56
Titanium Silicide Formation (TiSi2)
RC
RC
TiSi2
Poly Gate
RS
Rs’
RCH
RD’
RD
Figure 31: Transistor Cross section with Parasitic Resistances [14]
RTOTAL  RCHANNEL  RPARASITIC
Rs 'W  RSLDD Lspacer
RPARASITIC  REXTENSION  REXTRINSIC
REXTENSION  RS ' RD'
RD'W  RSLDD Lspacer
REXTRINSIC  RS  RD  2 RC
Rs  W  RSSILICIDE L
RD  W  RSSILICIDE L
RC  W 
Rochester Institute of Technology
Microelectronic Engineering

C
L
, C  2  10  9   cm 2
57
Titanium Silicide Formation (TiSi2)
o
Require < 10% reduction in drive current due to RPARASITIC
o
Sample calculation shown in Table #, assume:
o RS-LDD = 400 /sq
LSPACER = 0.25 um
o RS-Silcide = 4 /sq
LSILICIDE = 0.75 um
Table 7: Reduction in Drive Current due to Parasitic Resistance [14]
REXTENSION  W
REXTRINSIC  W
RPARASITIC  W
RSAT  W
( x m)
( x m)
( x m)
( x m)
RPARASITIC  W
RSAT  W
200
7
207
4108
5.1 %
o
All Resistances are calculated for a nominal 1 µm width
o
As width is increased, the total resistance components will decrease
but the ratio for drive current reduction will remain the same
o
Drive current is only reduced by ~5% by integrating silicide
Rochester Institute of Technology
Microelectronic Engineering
58
Titanium Silicide Formation (TiSi2)
o
Table 8 shows properties for Titanium Silicide reactions
Table 8: Titanium Silicide Properties [14]
Silicide
Thin Film Resistivity
(Ω-cm)
Sintering Temp
(C)
Stable on Si up to
(C)
Reaction with Al at
(C)
nm of Si
consumed
per nm of metal
nm of resulting silicide
per nm of metal
TiSi2 (C54)
TiSi2 (C49)
13-16
60-70
700-900
500-700
~900
450
2.27
2.27
2.51
2.51
o
45 nm of Si is consumed by 20 nm of Ti to produce 50 nm of TiSi2
in C49 phase
o
The C49 phase is a higher resistivity phase created after a 500700°C rapid thermal step
o
The unreacted Ti is removed by wet chemistry and a 2nd thermal
step is performed at 700-900°C to form lower resitivity C54 phase
o
50 nm of TiSi2 in the C54 phase should yield an Rs ~ 4 /sq
Rochester Institute of Technology
Microelectronic Engineering
59
Titanium Silicide Formation (TiSi2)
o
Titanium Silicide suffers from a narrow line width effect where Rs
increases as line width is decreased
o
This is why the industry transitioned to CoSi2 for sub-0.25 µm CMOS
Figure 32: Narrow Line Width Effect [9]
o
Intel reports an RS of 4 /sq for their 0.25 µm CMOS process, although
it is not reported if this is for the source/drain regions only, or gate too
o
Test structures will be designed on the test chip to observe this effect
Rochester Institute of Technology
Microelectronic Engineering
60
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
61
Contact Cut Etch
o
In a fully scaled 0.25 µm process, contact cut dimensions are
0.25 µm x 0.25 µm
o
Since Canon FPA-2000i1 stepper will be used, the smallest contact
cut dimensions will be 0.5 µm x 0.5 µm
o
Contact cuts below 2 µm x 2 µm must be dry etched since wet
chemistry acid will not go into small holes
o
Some devices will be designed with the smallest contact cuts that
must be plasma etched, while other devices will be designed with
larger contact cuts (2 µm or 5 µm) that can be wet etched
o
Loading is a fabrication phenomena where features with small areas
will take longer to clear then large areas.
o
It is desirable to have all contact cuts for a given design generation
to have the same area so that over-etch of smaller contacts will not
destroy regions with large areas that clear earlier
Rochester Institute of Technology
62
Microelectronic Engineering
Unit Process Development









Shallow Trench Isolation
Channel Engineering
 Uniformly Doped Twin Well
 Super Steep Retrograde Well
Ultra Thin Gate Oxide
Gate Formation
 Lithography
 Resist Trimming
 Reactive Ion Etch (RIE) of Gate
Source/Drain/Gate Doping
 Poly re-ox
 Low Doped Source/Drain Extensions
 Sidewall Spacers
 Source/Drain Contacts
 Dual Doped Poly
Rapid Thermal Dopant Activation
Titanium Salicide
Contact Cut Etch
2 Level Aluminum Metallization
Rochester Institute of Technology
Microelectronic Engineering
63
Aluminum Metallization
o
Multi level metal is necessary to build complex logic circuits that
require extensive routing while minimizing real estate
Aluminum
Nitride Spacers
P+ Poly
N+ Poly
P+ Well
Contact
STI
N+ S/D
LDD
P-SSRW
P-Well
P+ S/D
TiSi2
N+ Well
Contact
LDD
N-SSRW
N-Well
N-Substrate
Figure 33: 2 Level Aluminum Metallization
PECVD TEOS will be deposited as inter-level dielectric layer
o Aluminum will be sputter deposited to a thickness ~ 0.5 µm, then
patterned and etched by RIE in Chlorine chemistry
o A 2nd PECVD TEOS layer will be deposited to insulate Metal 1 from
Metal 2, this layer may undergo CMP to reduce topography
o Vias will be patterned and etched by RIE in Fluorine plasma
o Metal 2 will be sputter deposited to thickness ~ 1.0 µm, then
patterned and etched similarly to Metal 1
o
Rochester Institute of Technology
Microelectronic Engineering
64
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
65
Layout of Test Chip
Number Design Layer
1
2
3
4
5
6
7
8
9
Active
n-well
Poly
N+ select
P+ select
Contact cut
Metal 1
Via
Metal 2
Table 9: Test Chip Design Layers
Number Lithography Level
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STI
n-well
p-well
n-SSRW
p-SSRW
Poly
n-LDD
p-LDD
n+-S/D
p+-S/D
Contact cut
Metal 1
Via
Metal 2
1
2
3
4
5
6
7
8
9
10
Mask Level
STI
n-well
p-well
Re-use n-well
Re-use p-well
Poly
n-LDD select
p-LDD select
Re-use n-LDD select
Re-use p-LDD select
Contact cut
Metal 1
Via
Metal 2
A new test chip will be designed and mask set fabricated
o There are 9 design layers which will be used to create 10 photo masks
o These 10 photo masks will be used for 14 lithography levels
o In addition to transistors, logic circuits will be designed, as well as
capacitors for CV analysis, Van-der-pauw test structures for sheet
resistance measurements and Cross-Bridge Kelvin Resistor test
structures for measurement of contact resistances
o
Rochester Institute of Technology
Microelectronic Engineering
66
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
67
Integration/Fabrication/Test
o
Unit processes will be integrated into a full CMOS manufacturing flow
o
All fabrication will be done in the Semiconductor and Microsystems
Fabrication Laboratory (SMFL) at RIT
o
When fabrication is completed, the devices will be tested in the
Semiconductor Device Characterization lab at RIT
o
On and off-state performance will be characterized to qualify this process
o
Electrical parameter extraction will be performed to develop SPICE
models for this process which can be used in future circuit designs
o
The fabrication limits of the SMFL tool set will be pushed so that
custom design rules can be created for future layouts
Rochester Institute of Technology
Microelectronic Engineering
68
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
69
Time Line
ID
Task Name
1
Simulation
2
Process Development
3
Layout
4
Fabrication
5
Test
6
Thesis Writing
Spring 2005 Summer 2005
Fall 2005
Winter 2005
Spring 2006
Figure 34: Masters Thesis Time Line
o
This time line constitutes a reasonable plan of study to design,
fabricate and test 0.25 µm CMOS transistors
o
Ample time is left for thesis writing, review, and defense
Rochester Institute of Technology
Microelectronic Engineering
70
Outline









RIT/Industry Scaling Trends
Gate Control Fundamentals
Short Channel Effects
Deep-Submicron Scaling
Unit Process Development
Layout
Integration/Fabrication/Test
Time Line
Questions
Rochester Institute of Technology
Microelectronic Engineering
71
References
[1] M. Aquilino, “Advancing RIT to Submicron Technology: Design and Fabrication of 0.5 μm NMOS Transistors,” RIT Microelectronic Research Journal, 2004.
[2] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, pp. 114-117, 1965.
[3] “Microprocessor Quick Reference Guide.” http://www.intel.com/pressroom/kits/quickreffam.htm
[4] Y. Tsividis. Operation and Modeling of The MOS Transistor, 2nd Edition. Oxford University Press, 1999.
[5] S. E.Thompson, P. A.Packan, and M. T.Bohr, “Linear versus saturated drive current: Tradeoffs in super steep retrograde well engineering,” Symposium on VLSI Technology Digest,
pp. 154-155, 1996.
[6] L. Wilson, ed., “The National Technology Roadmap for Semiconductors: 1997 Edition”, Semiconductor Industry Association, San Jose, California
[7] De, I.; Osburn, C.M., “Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices,” IEEE Trans. Electron Devices, vol. 46, Issue: 8, pp.1711 - 1717, Aug.
1999
[8] R.C. Jaeger. Introduction to Microelectronic Fabrication, 2nd Edition. Prentice Hall, 2002.
[9] S. Wolf. Silicon Processing for the VLSI Era. Volume 4-Deep Submicron Process Technology. Lattice Press, 2002
[10] Q. Xu, “The investigation of key technologies for sub-0.1 μm CMOS device fabrication,” IEEE Trans. Electron Devices, vol. 48, pp. 1412-1420, July 2001.
[11] S. Thompson, P. Packan, M. Bohr, “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal, 1998.
[12] A. Brand, A. Haranahalli, N. Hsieh, Y.C. Lin, G. Sery, N. Stenton, B.J. Woo, S. Ahmed, M. Bohr, S. Thompson, S. Yang, “Intel’s 0.25 Micron, 2.0 Volts Logic Process Technology”, Intel
Technology Journal, 1998.
[13] “MOSIS SCMOS Technology Codes and Layer Maps SCNA and SCNE”, http://www.mosis.org/Technical/Layermaps/lm-scmos_scna.html
[14] http://www.stanford.edu/class/ee311/NOTES/Silicides.pdf
Rochester Institute of Technology
Microelectronic Engineering
72