Transcript vg_HiP_logic_reqt_table_jchung_presentation_0409

Draft Technology Table for High-Performance Logic
2001
130nm
65
2002
2003
53
45
Near Term
2004
90nm
37
1
1
2
nm
1.6
1.6
Electrical Thickness Adjustment
nm
0.8
Tox Equivalent (Electrical)
nm
2.0
Calendar Year
Technology Node
MPU Gate Length
Relative Dielectric Constant with
respect to Oxide
Tox Equivalent (Physical)
nm
Vdd
30
2007
65nm
25
2010
45nm
18
Long Term
2013
32nm
13
2
2
2
3
5
10
Set to limit short-channel effects
1.4
1.3
1.2
1.1
0.9
0.8
0.7
0.8
0.8
0.8
0.8
0.7
0.7
0.7
0.6
Set to limit gate tunneling current
Accounts for gate depletion and
inversion-layer quantum effects
1.8
1.5
1.5
1.4
1.3
1.0
0.9
0.7
2005
2006
32
2
1.5
0.8
2.0
Comments
2016
22nm
9
1.2
1.2
1.2
1.1
1.1
1.1
1
0.8
0.7
0.6
Sub-Threshold I-off
uA/um
0.01
0.03
0.07
0.1
0.3
0.7
1
3
7
10
"Effective" Gate Tunneling Current
uA/um
0.003
0.002
0.01
0.01
0.02
0.06
0.1
0.3
0.5
1
0%
0%
0%
0%
0%
0%
10%
35%
70%
115%
961
989
1118
1180
1252
1319
1431
1672
2069
2619
15%
16%
16%
16%
17%
18%
20%
24%
28%
33%
22%
27%
28%
28%
32%
32%
35%
39%
46%
52%
1.0
1.2
1.4
1.6
1.9
2.1
2.6
4.1
6.5
10.4
Required "Technology
Improvement" (SOI/LowTemp/High-mobility)
Id-NMOS
Rsd Percent of Channel R (Vdd/I)
Parasitic Capacitance Percent of
Cgate
Relative Device Performance
uA/um
1
Set by ORTC
Set only to maintainsufficient voltage
over-drive. Assume power
dissipation dealt with at the
design/system level.
Non-planar CMOS required at 65nm
node in order to control short-channel
effects
Limited to 10% of I-off. Assumes SiSiO2 tunneling model (needs
adjustment for different barrier
heights). Also sets the leakage limit
for other mechanisms (such as
junction leakage).
Set to maintain historical scaling
trend
PMOS assumed to scale similarly
Assumes 2X reduction in Rsd value
by 2016
Assumed constant value:
2.4e-16F/um
Based on CV/I metric
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Normalized Device Performance
High-Performance Logic Scaling (IEDM Comparison)
10.00
IEDM Benchmark Technologies
ITRS Projections
1.00
Historical Trend (17% per year)
0.10
1985
1990
1995
2000
2005
2010
2015
2020
Year




Benchmarks taken from IEDM publications; chose only technologies within 1-2 years of production.
IEDM Papers with leading-edge bulk (non-SOI) performance selected (Moto, TI, Intel).
Apparent discontinuity at year 2001 is an artifact due difference between IEDM publication date and
ITRS production node date.
17% historical trend is consistent with past IEDM data as well as with the previously used 2000 ITRS
projection for local-clock frequency.
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Scaling of Different Device Performance Factors
10.00
Normalized Change
Gate Length Reduction
Oxide Thickness Reduction
Power Supply Reduction
Transconductance Increase
Historical Trend
(17% per year)
1.00
2000
2005
2010
2015
2020
Year



Channel-length scaling has the greatest impact on continued device performance.
Power supply voltage can not be scaled as aggressively as other device performance factors in order
to maintain adequate overdrive (Vdd-VT).
New device technology improvements (SOI/low-temp/higher-mobility materials) will be needed to
achieve required transconductance increase in later years (in addition to Tox scaling).
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Scaling of Different Device Hazard Factors
Relative Increase
5.00
Gate Oxide E-Field
(Vdd/Tox)
4.00
Short-Channel Effects
(Tox/Lgate)
3.00
2.00
1.00
2000
Lateral High-Field Effects
(Vdd/Lgate)
2005
2010
2015
2020
Year



Gate-oxide effective E-field is increased by 50% by 2016.
Non-scalability of Tox/Lgate will increase short-channel effects. Project potential need for dual-gate
SOI devices by the 2007 (65nm) node.
Voltage non-scalability will result in significantly increased lateral high-field effects (mitigation of
these effects will be key device design challenge).
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Feedback to Other ITRS TWG Groups
 Design TWG:
•
•
•
Front-end performance can continue to scale at historical rate.
Both dynamic & static power dissipation must be dealt with at the
design and system level (not through Vdd scaling).
Circuit/system design must now account for significantly higher subthreshold and gate leakage current (devices approach bipolar-like
characteristics).
 Front-End-Process TWG:
•
•
•
•
•
•
Projection of Tox electrical requirements has been made.
Specification made for maximum gate-tunneling/junction leakage.
Scaling scenario proposed for high-K gate dielectrics.
Rsd allowed to become larger percentage of channel resistance;
however, still require 2X reduction in parasitic Rsd value by 2016.
Scaling scenario for gate electrode depletion has been proposed
(impacts metal gate introduction point).
Impact of parasitic fringe/overlap capacitance on device performance
has been evaluated (impacts gate stack aspect ratio and composition).
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