Transcript Lab1 - Tamu.edu

ECEN 248:
INTRODUCTION TO
DIGITAL SYSTEMS
DESIGN
Dept. of Electrical and Computer
Engineering
Describing Circuit Functionality:
Inverter
Truth Table
A
Y
A
Y
0
1
1
0
Symbol


Input
Basic logic functions have symbols.
The same functionality can be represented with truth
tables·

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Output
Truth table completely specifies outputs for all input
combinations.
The above circuit is an inverter.

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An input of 0 is inverted to a 1.
An input of 1 is inverted to a 0.
The AND Gate
A
B


This is an AND gate.
So, if the two inputs signals
are asserted (high) the
output will also be asserted.
Otherwise, the output will
be deasserted (low).
Y
Truth Table
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
The OR Gate
A
B


This is an OR gate.
So, if either of the two
input signals are
asserted, or both of
them are, the output
will be asserted.
Y
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
The NAND Gate

This is a NAND
gate. It is a
combination of an
AND gate followed
by an inverter. Its
truth table shows
this.
A
B
Y
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
The NOR Gate
A
B

Y
This is a NOR gate. It is a combination
of an OR gate followed by an inverter.
A
B
It’s truth table shows this
Y
0
0
1
0
1
0
1
0
0
1
1
0
The XOR Gate (Exclusive-OR)
A
B



Y
This is a XOR gate.
XOR gates assert their output
when exactly one of the inputs
is asserted, hence the name.
The switching algebra symbol
for this operation is , i.e.
1  1 = 0 and 1  0 = 1.
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
ECEN 248
Introduction to Digital Design Lab
Dept. of Electrical and Computer
Engineering
Lab Details
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http://ece.tamu.edu/~ysy6529
Lab Policies
Issue of Components (Room 111A) – Before
Lab Class
Structure of Lab - Breadboarding and Verilog
Tips & Tricks of Breadboarding
Prelab & Postlab Deliverables
Feedback Form
Some Important Rules

Deliverables:
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Prelabs (typed, short and concise) are due at the
beginning of each lab. All your designs should be ready.
Get TAs help during office hours, if you need help on your
design.
Postlabs are due at the beginning of next lab.
Download, Print and Keep the following:
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Lab Manual:
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Syllabus, Lab Policy Document- Breadboard tip & tricks
Lab details
Appendix A, B
Misc
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Labs stay open till 9:00PM. Use free lab times to complete
the lab work. Arrange meeting with TA for any help.
Instruments in the Lab
1.BreadBoard
Vertical
Direction
IC’s should be
placed across
the split
Split 1
Ground
Line
PARTITION 1
IC
notch
PARTITION 2
These 2
lines are
not shorted
PARTITION 3
PARTITION 4
Power
Line
These 2
lines are
not shorted
Line of
Pins Short
Together
Horizontal
Direction
Split 2
Instruments in the Lab
2.Multimeter
2.Oscilloscope
Instruments in the Lab
4.Power Supply
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Please talk to the TA if there is any doubt regarding
the use of instruments. A detailed description of
each instrument is given in the Tips and Tricks of
Breadboarding Section.
For IC pin numbers, refer to Appendix A
Lab # 1 in Brief
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Study of Standard Gates
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Inverter Transfer Characteristics
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Study the standard 2-input gates given in manual
Plotting the input vs output voltage for an inverter
Ring Oscillator
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A ring of inverters as a clock signal
Use 5 inverters back to back as shown in Manual
Lab # 2: Logic Minimization and K-Maps
Details and Hints
H
C
S
I
a
Profit
Computer
P0
D
b
P1
Seven
Segment
B Driver
A
c
P2
C
a
f
b
g
d
e
f
g
e
c
d
Seven-Segment
Display
1. Draw three K-Maps, one for each output
for the Profit Computer based on the
information in the Farm problem
2. Connect BCD to Seven Segment as
shown
3. Connect Seven Segment Display
Deadline
First week:
Postlab of Lab # 1, part1 is due in class next week.
Second week
Postlab of Lab # 1, part2 is due in class next week.
Prelab for Lab # 2 is due in class next week.