Transcript Drawbacks of Metal-gate MOS Transistors

EE 4345
Semiconductor Electronics
Design Project
CMOS Process
Mohammad Butt
Ahmad Elmardini
Devices
Heithem Souissi
Dina Miqdadi
Process Extension
Fares Alnajjar
Wyatt Sullivan
CMOS Process
Drawbacks of Metal-gate MOS
Transistors
• Metal-gate PMOS transistors cannot maintain the
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minimal(+0.5V) threshold variation.
Excess surface state charges and mobile ion
contamination are two main sources of threshold
variation.
Suffer from excessive overlap capacitance.
Parasitic capacitances Cgs and Cgd slow the
transistor because they must be charged and
discharged during switching.
Aluminum is used as gate material which can
erode completely causing contact spiking.
Features of Polysilicon-gate
CMOS Process
• Consists of nine masking steps
• Optimized to form complementary PMOS and
NMOS transistors on a common substrate
• Can also fabricate some analog circuits with slight
modifications
• Use (100) silicon to reduce surface state density
and improve threshold voltage control
• Polysilicon-gate is doped with phosphorus to
minimize mobile ion contamination, resulting in
faster switching speeds and better control of
threshold voltage
Oveview of Polysilicon-gate
CMOS Process
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Start with P-substrate
Grow P-type epitaxial layer on the substrate
Create N-well regions and channel stop regions
Grow gate oxide (thin oxide) and field oxide
(thick oxide)
• Deposit and pattern polysilicon layer
• Implant source and drain regions, substrate
contacts
• Create contact windows, deposit and pattern metal
layer
Epitaxial Growth
• P-type substrate is doped with as much
boron as possible to minimize substrate
resistivity
• Lightly doped P-type epitaxial layer is
grown on substrate
• NMOS transistors are formed directly on
the epi layer which serves as a backgate
P-epi
P-substrate
N-well Diffusion
• The wafer is then oxidized and etched to
open windows through which ion
implantation deposits a controlled dose of
phosphorus
• A prolonged drive creates a deep lightly
doped N-type region called N-well
• Thermal oxidation covers the exposed
silicon with thin layer of pad oxide
N-well Diffusion
• In N-well CMOS process, NMOS
transistors occupy the epi and PMOS
transistors reside in well. This process
optimizes NMOS at the expense of PMOS
P-epi
P-substrate
pad oxide
N-well
P-well Diffusion
• P-well CMOS process uses N+ substrate
and N- epitaxial layer and a P-well. NMOS
transistors are formed in P-well and PMOS
transistors in the epi. This process optimizes
PMOS at the expense of NMOS
N-epi
N-substrate
pad oxide
P-well
Why N-well CMOS Process?
• The N-well process offers a slightly better
NMOS transistor than P-well CMOS and
also allows the use of a grounded substrate
favored by most circuit designers.
• In a P-well process the NMOS still
outperforms its counterpart because
electrons are more mobile than holes
Inverse Moat
• LOCOS process is used to define field
regions and moat regions
• Locally oxidized regions of the die are
called ‘field regions’
• Areas protected from oxidation are called
‘moat regions’
• First a patterned nitride layer is formed by
depositing nitride across entire wafer
Inverse Moat (cont.)
• A selective etch is used to remove nitride over the
field regions
• The photomask used is called inverse moat mask
because it codes for areas where moat is absent
photoresist
nitride
P-epi
P-substrate
pad oxide
N-well
Channel Stop Implants
• Channel stop implants are required to ensure that
thick-field threshold exceed the operating voltages
• It uses a boron implant followed by a patterned
phosphorus implant
• Phosphorus implant counterdopes boron implant
and raises NMOS thick-field threshold above
maximum operating voltage
Channel Stop Implants (cont.)
• After LOCOS oxidation, a suitable etching strips
away the remnants of the nitride block mask
• Curved transition region at the edges of moat
results from oxidants diffusing under the edges of
nitride film and is called ‘bird’s-beak’
• All photoresist is stripped off from the wafer in
preparation for LOCOS oxidation
Channel Stop Implants (cont.)
• A thin layer of oxide called ‘dummy gate
oxide’ is grown in moat regions to eliminate
any nitride formed underneath the pad oxide
due to ‘kooi effect’
photoresist
nitride
Boron channel stop
P-epi
P-substrate
Phosphorus channel stop
pad oxide
N-well
Threshold Adjust
• Method 1: Two separate implants to set
PMOS Vt and NMOS Vt. This Method
allows independent optimization of both
thresholds
• Method 2: Single Vt adjust implant to
simultaneously reduce PMOS threshold and
increase NMOS threshold
Threshold Adjust (cont.)
• The boron Vt adjust implant penetrates of the
dummy gate oxide to dope underlying silicon
• After the Vt adjust implant, dummy gate oxide is
stripped away to reveal bare silicon in moat
regions
Dummy gate oxide
Field oxide
Boron channel stop
P-epi
P-substrate
Phosphorus channel stop
N-well
Boron Vt adjust implant
Polysilicon Deposition and
Patterning
• Polysilicon layer used to form gate
electrodes is heavily doped with phosphorus
to reduce its resistivity
• The deposited polysilicon layer is patterned
using polymask
Gate oxide
poly
Boron channel stop
Phosphorus channel stop
Field oxide
P-epi
P-substrate
N-well
Boron Vt adjust implant
Source/Drain Implants
• NSD implant involves application of photoresist to
the wafer, followed by patternig using the NSD
mask
• Heavily doped N-types regions are formed by
implanting ardenic through exposed gate oxide
• Photoresist residue is stripped off and a new
photoresist layer is patterned using PSD mask
Source/Drain Implants (cont.)
• Heavily doped P-type region is formed by
implanting Boron through exposed gate
oxide
• Photoresist is again stripped off and a brief
anneal activates the implanted dopants
Gate oxide
poly
PSD
NSD
Field oxide
P-epi
P-substrate
N-well
Contacts
• MLO (Multilevel Oxide) is deposited and
the wafer is again coated with photoresist
• Contact windows are created and silicide is
formed in the contact openings
• Thin film of refractory metal precedes a
much thicker layer of copper doped
aluminium
Protective Overcoat
• Protective overcoat is deposited over the
final layer of metallization to provide
mechanical protection and to prevent
contamination of the die
• Selected areas of metallization are etched to
attach bondwires to the integrated circuit
Devices
Transistor structure
Transistor (Bell Labs)
Transistor Layout
Gate Voltage and The Channel
Basic Transistor Parasitic
P-Channel MOSFET
N-Channel MOSFET
Layout and cross section of PNP
substrate transistor
PSD/NSD Resistors
MOSFET Capacitances
• capacitances have three origins:
– The basic MOS structure
– The channel charge
– The pn-junctions depletion regions
Gate
Source
CGS
Drain
CGB
CSB
CGD
CDB
Bulk
Process Extension
Process Extension
• CMOS process extension tend to focus on
improving the PMOS and NMOS transistors.
• Types:
- One set seeks to provide higher operating voltages.
- Another focuses on reducing the size of the transistor.
Process Extension
Double-level Metal
• -It adds two steps to the process: one vias and
One for metal-2
• Interlevel oxide(ILO) is deposited between the
Two metal layers
-This provides insulation
-The planarization improves for the second
Level
Process Extension
Double-level Metal(cont.)
• Process extension.
• The extra processing steps increase the cost
of the wafer.
• Use of extra metal layers would reduce the
area required for interconnection in high
density auto routed logic.
Process Extension
Double-level Metal(cont.)
• Advantages of more levels of metal
interconnect,2,3,4,etc:
-Eases automated routing and improves power
and clock distribution to modules.
-Vias are used to connect upper layers of
metal to metal 1.
-”Contact cuts” are made from metal 1 to
diffusion or poly.
Process Extension
Double-level Metal(cont.)
Process Exention
Silicidation
• Silicidation: an anneal(sintering) resulting in the
formation metal-Si alloy to act as a contact.
• Used for:
1.Reducing sheet resistance.
-Poly resistances between 20 and 40 ohms.
-Silicide (silicon and tantalum) used as gate material,
between 1 and 5 ohms.
-Can be extended to source and drain, called.
salicide.
Process Extension
Silicidation(cont.)
Process Extension
Lightly Doped Drain Transistors
• Designed to minimize hot-carriee effects; The
reduced doping gradient between drain and
channel lower electric field.
• Implementation: typical NMOS with 3mm length
operate within 5-10V, PMOS with the same
dimensions can withstand 15-20 V. That’s where
the LDD comes in handy.
• LDD can withstand substantially higher drain-tosource voltage than the singly doped drain
(SDD)devices.
Process Extension
LDD(cont.)
• Use of two drain diffusions:
-One forming a lightly doped drift region near
the edge of the gate.
-The other forming a more heavily doped
region beneath the contact, this will reduce
the drain resistance of the structure and
allows the transistor to retain most of the
performance of a conventional SDD device.
Process Extension
LDD(cont.)
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Process to form LDD transistors:
Use of an oxide sidewall spacer to selfalign the two drain diffusions, therefore,
enabling precise control of the width of
the drift region.
Process Extension
LDD(cont.)
• Fabrication steps:
1. A shallow implant self-aligned to the edges of the
gate polysilicon deposits the lightly doped drain.
2. The wafer is coated with a thick layer of
isotropically deposited oxide.
3. Use anisotropic dry etch to remove most of the
deposited oxide.
4. A second drain implant self-aligned to the edges of
the oxide sidewall spacers to form the heavily
doped portions of the LDD.
Process Extension
LDD(cont.)
Advantages:
 Improves tolerability of high drain-tosource voltages.
 Does not increase real-estate needed.
 Provides greater depletion regions widths,
which in turn, provides better tolerances to
hot carrier degradation.
Process Extension
LDD(cont.)
• Drawbacks:
Requires additional masks to selectively
block N-S/D implants
Slightly increases drawn channel
lengths(0.5-1m)
Extended-drain, High-voltage
Transistors
• Potentially can withstand in excess of 30 V.
• Uses existing masks of standard n-well polyCMOS process.
• Drawbacks:
-Inherently long channel devices.
-High overlap capacitance.
-Asymmetric.
-Higher susceptibility to oxide rupture( decreases device
transconductance).
Extended-drain, High-voltage
Transistors
Extended-Drain, Highvoltage(cont).
Extended-Drain, High
Voltage(cont).
References
• The Art of Analog Layout, by Alan Hastings
• Semiconductorglossary.com
• http://www.iue.tuwien.ac.at/publications/PhD
%20Theses/puchner/node36.html
• http://www.sse.uu.se/education/acad/pdf/2000/
Design_Rules.pdf
• http://vlsi.wpi.edu/webcourse/ch02/ch02.html