Transcript Combinational Networks 1

Topics

Transistor sizing:
– Spice analysis.
– Logical effort.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Transistor sizing
Not all gates need to have the same delay.
 Not all inputs to a gate need to have the
same delay.
 Adjust transistor sizes to achieve desired
delay.

Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Example: adder carry chain
One stage:
+
ai
bi
ai
bi
+
ci
c i+1
ai
Modern VLSI Design 4e: Chapter 4
ci
ai
bi
bi
Copyright  2008 Wayne Wolf
Carry chain optimization
Connect four stages.
 Optimize delay through carry chain by
selecting transistor sizes.

Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Case 1
W/L for all stages: n = 270/180 nm, p = 540/180 nm
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Case 2 circuit



a, b, c pulldowns are
540/180 nm.
First stage inverter
pullup is 1620/180
nm, pulldown is
540/180 nm.
Later state inverters
have
pullups/pulldowns of
540/180 nm.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Case 2
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Case 3 circuit



a, b pulldowns are
270/180 nm.
c pulldown is
1080/180 nm.
First stage inverter
pullup is 1620/180
nm, pulldown is
540/180 nm.
Modern VLSI Design 4e: Chapter 4

Later state inverters
have pullups of
1080/180 nm,
pulldowns of 540/180
nm.
Copyright  2008 Wayne Wolf
Case 3
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Inter-stage effects in transistor
sizing

Increasing a gate’s drive also increases the
load to the previous stage:
Larger
load
Modern VLSI Design 4e: Chapter 4
Larger
drive
Copyright  2008 Wayne Wolf
Logical effort
Logical effort is a gate delay model that
takes transistor sizes into account.
 Allows us to optimize transistor sizes over
combinational networks.

– Isn’t as accurate for circuits with reconvergent
fanout.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Logical effort gate delay model
Gate delay is measured in units of
minimum-size inverter delay t.
 Gate delay formula:

– d = f + p.
Effort delay f is related to gate’s load.
 Parasitic delay p depends on gate’s
structure.

Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Effort delay

Effort delay has two components:
– f = gh.

Electrical effort h is determined by gate’s
load:
– h = Cout/Cin

Logical effort g is determined by gate’s
structure.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Logical effort
1 input
2 inputs
3 inputs
4 inputs
n inputs
NAND
4/3
5/3
6/3
(n+2)/3
NOR
5/3
7/3
9/3
(2n+1)/3
mux
2
2
2
2
inverter
1
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Logical effort along a path

Logical effort along a chain of gates:
– G = P gi .

Total electrical effort along path depends on
ratio of first and last stage capacitances:
– H = Cout/Cin.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Branching effort
Takes into account fanout.
 Branching effort at one stage:

– b = (Conpath + Coffpath/ Conpath)

Branching effort along path:
– B = P bi.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Path delay

Path effort:
– F = GBH.

Path delay is sum of delays of gates along
the path:
– D = S gi hi + S pi = DF + P.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Sizing the transistors

Optimal buffer chains are exponentially
tapered:
– f^ = F 1/N.

Determine W/L of each gate on path by
working backward from the last gate:
– C in,i = gi C out,i / f^
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Example: logical effort

Size transistors in a chain of three two-input
NAND gates.
– First NAND is driven by minimum-size
inverter.
– Last NAND is connected to 4X inverter.
Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf
Example, cont’d.
Logical effort G = 4/3 * 4/3 * 4/3.
 Branching effort = 1.
 Electrical effort = 4.
 F = G B H = 9.5.
 Optimum effort per stage f^ = 2.1.

Modern VLSI Design 4e: Chapter 4
Copyright  2008 Wayne Wolf