Transcript Architecture Design 1

Topics
•
Modeling with hardware description
languages (HDLs).
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Hardware description languages
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Textual languages for describing hardware:
– structure;
– function.
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Most people today use textual languages
rather than schematics for most digital
design.
– Schematics make poor use of screen space.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Major HDLs
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Two major HDLs designed for simulation:
– VHDL;
– Verilog.
– Similar capabilities but somewhat different
language philosophies.
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EDIF is a standard netlist format.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Simulation vs. programming
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Simulation tags computations with times.
– Must know when signals change to properly
simulate hardware.
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Simulation is parallel.
– Many statements can execute at the same
(simulation) time.
– Just like hardware.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Types of simulation
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Compiled code simulation.
– Generate program that evaluates a hardware
block.
– Operational details within the hardware block
are lost.
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Event-driven simulation.
– Propagate events through simulation.
– Don’t simulate a block until its inputs change.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
•
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An event is a change
in a net’s value.
An event has two
components:
– value;
– time.
net1
Event-driven simulation
t=35 ns
time
net
net1=0 @ 35 ns
event
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
•
•
Propagate events
only when nets
change value.
If an input change
doesn’t cause an
output change, no
event is propagated.
Modern VLSI Design 4e: Chapter 8
0
1
1
0
1 no0
event
Copyright  2008 Wayne Wolf
Timewheel
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•
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The timewheel is a data structure in the
simulator that efficiently determines the
order of events processed.
Events are placed on the timewheel in time
order.
Events are taken out of the head of the
timewheel to process them in order.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Timewheel operation
c=0 @ 2 ns
a
c
1
0
1
0
b=1 @ 1 ns
time
1
b
a=1 @ 0 ns
netlist
Modern VLSI Design 4e: Chapter 8
timewheel
Copyright  2008 Wayne Wolf
Order of evaluation
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Order of evaluation is important.
– Causality must be obeyed.
•
Evaluating events in the wrong order can
cause inaccurate results.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Order of evaluation example
a
0
0
e=0 @ 4 ns
c 1
1
1
b
0
1
d
netlist
Modern VLSI Design 4e: Chapter 8
e
0
d=1 @ 2 ns
time
b=1 @ 1 ns
timewheel
Copyright  2008 Wayne Wolf
Modeling
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Structural modeling describes the
connections between components.
– Netlists are structural models.
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Behavioral models describes the functional
relationship between inputs and outputs.
– Similar to programming but values are events.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
HDLs language constructs
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Must be able to define component types.
– A model may be behavioral or structural.
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May be able to define abstract data types.
– A wire may carry an enumerated value.
– Multi-valued simulation may be defined using
abstract data types.
•
May be able to define modules to control
the scope of names.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Testbenches
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A testbench is a model used to exercise a
simulation.
– Provides stimulus.
– Checks outputs.
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Testbenches help automate design
verification.
– Rerun edited module against testbench.
– Run models at behavioral, RTL levels against
the same testbench.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Synthesis subsets
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VHDL and Verilog were designed for
simulation.
A synthesis subset is:
– synthesizable;
– produces consistent simulation results.
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Different tools may use different synthesis
subsets.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Register-transfer synthesis
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Most common type of synthesis.
Synthesizes gates from abstract RT model.
– Registers are explicit.
– Some tools will infer storage elements---be
careful.
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Optimized for performance, area, power.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf