Transcript Combinational Gates 4

Topics
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Pseudo-nMOS gates.
DCVS logic.
Domino gates.
Design-for-yield.
Gates as IP.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Pseudo-nMOS
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Uses a p-type as a resistive pullup, n-type
network for pulldowns.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Characteristics
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Consumes static power.
Has much smaller pullup network than
static gate.
Pulldown time is longer because pullup is
fighting.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Output voltages
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Logic 1 output is always at VDD.
Logic 0 output is above Vss.
VOL = 0.25 (VDD - VSS) is one plausible
choice.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Producing output voltages
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For logic 0 output, pullup and pulldown
form a voltage divider.
Must choose n, p transistor sizes to create
effective resistances of the required ratio.
Effective resistance of pulldown network
must be comptued in worst case—series ntypes means larger transistors.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Transistor ratio calculation
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In steady state logic 0 output:
– pullup is in linear region,Vds = Vout - (VDD VSS) ;
– pulldown is in saturation.
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Pullup and pulldown have same current
flowing through them.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Transistor ratio, cont’d.
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Equate two currents:
– Idp = Idd.
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Using 0.5 mm parameters, 3.3V power
supply:
– Wp/Lp / Wn/Ln = 3.9.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
DCVS logic
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DCVSL = differential cascode voltage
logic.
Static logic—consumes no dynamic power.
Uses latch to compute output quickly.
Requires true/complement inputs, produces
true/complement outputs.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
DCVS structure
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
DCVS operation
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Exactly one of true/complement pulldown
networks will complete a path to the power
supply.
Pulldown network will lower output
voltage, turning on other p-type, which also
turns off p-type for node which is going
down.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
DCVS example
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Precharged logic
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Precharged logic uses stored charge to help
evaluation.
Precharge node, selectively discharge it.
Take advantage of higher speed of n-types.
Requires multiple phases for evaluation.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino logic
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Uses precharge clock to compute output in
two phases:
– precharge;
– evaluate.
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Is not a complete logic family—cannot
invert.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino gate structure
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino phases
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Controlled by clock .
Precharge: p-type pullup precharges the
storage node; inverter ensures that output
goes low.
Evaluate: storage node may be pulled down,
so output goes up.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino buffer
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Output inverter is needed for two reasons:
– make sure that outputs start low, go high so that
domino output can be connected to another
domino gate;
– protects storage node from outside influence.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino operation
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino effect
Gate outputs fall in sequence:
gate 1
Modern VLSI Design 4e: Chapter 3
gate 2
gate 3
Copyright  2008 Wayne Wolf
Monotonicity
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Domino gates inputs must be monotonically
increasing: glitch causes storage node to
discharge.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Output buffer
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Inverting buffer isolates storage node.
Storage node and inverter have correlated
values.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Using domino logic
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Can rewrite logic expression using De
Morgan’s Laws:
– (a + b)’ = a’b’
– (ab)’ = a’ + b’
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Add inverters to network inputs/outputs as
required.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Domino and stored charge
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Charge can be stored in source/drain
connections between pulldowns.
Stored charge can be sufficient to affect
precharge node.
Can be averted by precharging the internal
pulldown network nodes along with the
precharge node.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Design-for-yield
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Design processes that improve chip yield in
very deep submicron/nanometer
technologies.
Must treat design and manufacturing as a
unified processing to maximize yield in
nanometer technologies.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Variations in manufacturing
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Three types of variations:
– Systematic variations can be predicted based on
design and mask information plus
manufacturing equipment.
– Random variations include variations in
parameters, etc.
– Environmental variations include temperature,
etc.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Trends in manufacturing
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Larger variations in process and circuit
parameters.
Higher leakage currents.
Patterning problems caused by specific
combinations of geometric features.
Metal width and thickness variations.
Stress in vias.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Design-for-yield examples
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Lithographic simulation to find yield
problems not covered by standard design
rules.
Extra vias added to increase the reliability
of connections.
Statistical timing analysis to identify
problems caused by variations in wiring.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Gates as IP
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The standard cell library was one of the first
forms of IP.
– Reusable across many chips.
– Portable from one process to another.
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Standard cell compatibility issues:
– Layout: cell size, pin placement.
– Delay: driving specified load.
– Power consumption.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Standard cell physical design
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Basic cell organization is dictated by
placement and routing system.
All cells are the same height.
– May be one of a set of standard widths.
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Pins must be placed on routing grid, usually
determined by wiriing layers used.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Standard cell logical design
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Must support a Boolean complete set of
functions.
Should support enough gate types for good
logic synthesis results.
Need several electrical variations of each
function:
– Low power.
– High speed.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Cell verification and qualification
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Cells are verified by layout extraction and
circuit simulation.
– Simulate a variety of process parameter
combinations.
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Qualification requires fabrication of cells on
the target process.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf