Transcript Architecture Design 2

Topics
•
•
•
High-level synthesis.
Architectures for low power.
GALS design.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
High-level synthesis
•
•
•
Sequential operation is not the most
abstract description of behavior.
We can describe behavior without
assigning operations to particular clock
cycles.
High-level synthesis (behavioral synthesis)
transforms an unscheduled behavior into a
register-transfer behavior.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Tasks in high-level synthesis
•
•
Scheduling: determines clock cycle on
which each operation will occur.
Binding (allocation): chooses which
function units will execute which
operations.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Functional modeling code in
VHDL
o1 <= i1 or i2;
if i3 = ‘0’ then
o1 <= ‘1;
o2 <= a + b;
else
o1 <= ‘0’;
end if;
Modern VLSI Design 4e: Chapter 8
clock cycle boundary can
be moved to design different
register transfers
Copyright  2008 Wayne Wolf
Data dependencies
•
Data dependencies describe relationships
between operations:
– x <= a + b; value of x depends on a, b
•
High-level synthesis must preserve data
dependencies.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Data flow graph
•
•
•
•
Data flow graph (DFG) models data
dependencies.
Does not require that operations be
performed in a particular order.
Models operations in a basic block of a
functional model—no conditionals.
Requires single-assignment form.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Data flow graph construction
original code:
x <= a + b;
y <= a * c;
z <= x + d;
x <= y - d;
x <= x + c;
Modern VLSI Design 4e: Chapter 8
single-assignment form:
x1 <= a + b;
y <= a * c;
z <= x1 + d;
x2 <= y - d;
x3 <= x2 + c;
Copyright  2008 Wayne Wolf
Data flow graph construction,
cont’d
Data flow forms directed acyclic graph
(DAG):
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Goals of scheduling and
allocation
•
•
•
Preserve behavior—at end of execution,
should have received all outputs, be in
proper state (ignoring exact times of
events).
Utilize hardware efficiently.
Obtain acceptable performance.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Data flow to data path-controller
One feasible schedule for last DFG:
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Binding values to registers
registers fall on
clock cycle
boundaries
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Choosing function units
muxes allow
function units
to be shared
for several
operations
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Building the sequencer
sequencer requires three states,
even with no conditionals
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Choices during high-level
synthesis
•
•
•
Scheduling determines number of clock
cycles required; binding determines area,
cycle time.
Area tradeoffs must consider shared
function units vs. multiplexers, control.
Delay tradeoffs must consider cycle time
vs. number of cycles.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Finding schedules
•
Two simple schedules:
– As-soon-as-possible (ASAP) schedule puts
every operation as early in time as possible.
– As-late-as-possible (ALAP) schedule puts
every operation as late in schedule as possible.
•
Many schedules exist between ALAP and
ASAP extremes.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
ASAP and ALAP schedules
ASAP
ALAP
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Critical path of schedule
Longest path through data flow determines
minimum schedule length:
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Operator chaining
•
•
May execute several
operations in sequence in one
cycle—operator chaining.
Delay through function units
may not be additive, such as
through several adders.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Control implementation
•
•
•
Clock cycles are also known as control
steps.
Longer schedule means more states in
controller.
Cost of controller may be hard to judge
from casual inspection of state transition
graph.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Controllers and scheduling
functional
model:
x <= a + b;
y <= c + d;
one state
two states
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Distributed control
two distributed controllers
one centralized controller
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Synchronized communication
between FSMs
To pass values between two machines, must schedule output
of one machine to coincide with input expected by the other:
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Hardwired vs. microcoded
control
•
•
•
Hardwired control has a state register and
“random logic.”
A microcoded machine has a state register
which points into a microcode memory.
Styles are equivalent; choice depends on
implementation considerations.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Data path-controller delay
Watch out for long delay paths created by
combination of data path and controller:
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Architectures for low power
•
Power controller
examines system
state, controls
subsystems.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Power-down modes
•
CMOS doesn’t consume power when not
transitioning. Many systems can
incorporate power-down modes:
– condition the clock on power-down mode;
– add state to control for power-down mode;
– modify the control logic to ensure that powerdown/power-up don’t corrupt control state.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Gate power control
•
Some gate types have low power modes.
– Sleep transistor.
•
Can also change substrate voltage in a
region.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Data latching
•
•
•
Store data in registers to avoid glitching in
combinational logic.
Use conditional clocks on existing latches
to hold data when not in use.
Avoid improper use of dynamic storage.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Clock gating
•
•
•
Clock gating can cause clocked logic to
freeze state.
Must make sure that logic operates
properly when frozen, when turned back
on.
Must carefully design clock network with
gating to avoid skew, etc.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Architecture-driven voltage
scaling
•
•
Add extra logic to increase parallelism so
that system can run at lower rate.
Power improvement for n parallel units
over Vref:
– Pn(n) = [1 + Ci(n)/nCref + Cx(n)/Cref](V/Vref)
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Architecture-driven voltage
scaling
before
after
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Dynamic voltage and frequency
scaling
•
Technique for microprocessors:
– Control power supply voltage and clock.
– Clock frequency must be in legal range for
power supply voltage setting.
•
•
Relies on dynamic workload--microprocessor may not need to run at full
speed.
DVFS controller sets power supply, clock.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
GALS design
•
•
Globally asynchronous, locally
synchronous design uses different clock
domains for different parts of the chips.
Styles:
– Pausable clocks.
– Asynchronous interfaces.
– Loosely synchronous interfaces.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
GALS structure
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf