Transcript Combinational Gates 3

Topics
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Wire delay.
Buffer insertion.
Crosstalk.
Inductive interconnect.
Switch logic.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Wire delay
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Wires have parasitic resistance, capacitance.
Parasitics start to dominate in deepsubmicron wires.
Distributed RC introduces time of flight
along wire into gate-to-gate delay.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RC transmission line
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Assumes that dominant capacitive coupling
is to ground, inductance can be ignored.
Elemental values are ri, ci.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Elmore delay
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Elmore defined delay through linear
network as the first moment of the network
impulse response.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RC Elmore delay
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Can be computed as sum of sections:
E =  r(n - i)c = 0.5 rcn(n-1)
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Resistor ri must charge all downstream
capacitors.
Delay grows as square of wire length.
Minimizing rc product minimizes growth of
delay with increasing wire length.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RC transmission lines
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More complex analysis.
Step response:
– V(t) @ 1 + K1 exp{-s1t/RC}.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Wire sizing
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Wire length is determined by layout
architecture, but we can choose wire width
to minimize delay.
Wire width can vary with distance from
driver to adjust the resistance which drives
downstream capacitance.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Optimal wiresizing
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Wire with minimum delay has an
exponential taper.
Optimal tapering improves delay by about
8%.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Approximate tapering
Can approximate optimal tapering with a few
rectangular segments.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Tapering of wiring trees
Different branches of tree can be set to
different lengths to optimize delay.
source
sink 1
sink 2
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Spanning tree
A spanning tree has segments that go directly
between sources and sinks.
source
sink 1
sink 2
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Steiner tree
A Steiner point is an intermediate point for the
creation of new branches.
source
Steiner point
sink 1
sink 2
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RC trees
Generalization of RC transmission line.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Buffer insertion in RC
transmission lines
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Assume RC transmission line.
Assume R0 is driver’s resistance, C0 is
driver’s input capacitance.
Want to divide line into k sections of length
l. Each buffer is of size h.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Buffer insertion analysis
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Assume h = 1:
– k = sqrt{(0.4 Rint Cint)/(0.7R0 C0)}
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Assume arbitrary h:
– k = sqrt{(0.4 Rint Cint)/(0.7R0 C0)}
– h = sqrt{(R0 Cint)/(Rint C0)}
– T50% = 2.5 sqrt{R0 C0 Rint Cint}
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Buffer insertion example
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Minimum-size inverter drives metal 1 wire
of 2000 l x 3 l.
– R0 = 3.9 kW, C0 = 0.68 fF, Rint = 53.3 kW, Cint =
105.1 fF.
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Then
– k = 1.099.
– H = 106.33.
– T50% = 9.64 E-12
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RC crosstalk
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Crosstalk slows down signals---increases
settling noise.
Two nets in analysis:
– aggressor net causes interference;
– victim net is interfered with.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Aggressors and victims
aggressor net
victim net
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Wire cross-section
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Victim net is surrounded by two aggressors.
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aggressor
W
T victim
aggressor
H
substrate
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
relative RC delay
Crosstalk delay vs. wire aspect
ratio
increased spacing
Increasing aspect ratio
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Crosstalk delay
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There is an optimum wire width for any
given wire spacing---at bottom of U curve.
Optimium width increases as spacing
between wires increases.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
RLC transmission lines
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Most results come from curve fitting.
Propagation delay is largely a factor of x.
50% propagation delay can be calculated in
terms of x.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Kahng/Muddu model
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Analytical model of similar complexity to
Elmore model.
Let Rs, Ls be source impedance, Rint, Cint,
Lint be transmission line impedance, CL be
load impedance.
Delay t = KC 2b2/sqrt(4b2 – b12), KC usually
1.66.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Switch logic
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Can implement Boolean formulas as
networks of switches.
Can build switches from MOS transistors—
transmission gates.
Transmission gates do not amplify but have
smaller layouts.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Types of switches
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Behavior of n-type switch
n-type switch has source-drain voltage drop
when conducting:
– conducts logic 0 perfectly;
– introduces threshold drop into logic 1.
VDD
VDD - Vt
VDD
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
n-type switch driving static logic
Switch underdrives static gate, but gate
restores logic levels.
VDD
VDD - Vt
VDD
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
n-type switch driving switch
logic
Voltage drop causes next stage to be turned on
weakly.
VDD
VDD - Vt
VDD
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Behavior of complementary
switch
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Complementary switch products full-supply
voltages for both logic 0 and logic 1:
– n-type transistor conducts logic 0;
– p-type transistor conducts logic 1.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Layout characteristics
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Has two source/drain areas compared to one
for inverter.
Doesn’t have gate capacitance.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf